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MSM6948-3V

Features: • Signal power supply: +3.6 V• On-chip SCF (Switched Capacitor Filter)• The transmit filter can be also used as voice splatter filter.• The receive timing re-generator has two different lock-in time performance options to be chosen from.• Built-in crystal os...

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SeekIC No. : 004429074 Detail

MSM6948-3V: Features: • Signal power supply: +3.6 V• On-chip SCF (Switched Capacitor Filter)• The transmit filter can be also used as voice splatter filter.• The receive timing re-genera...

MSM6948-3V Data Sheet

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Part Number:
MSM6948-3V
Supply Ability:
5000

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  • 1~5000
  • Unit Price
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  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Signal power supply: +3.6 V
• On-chip SCF (Switched Capacitor Filter)
• The transmit filter can be also used as voice splatter filter.
• The receive timing re-generator has two different lock-in time performance options to be chosen from.
• Built-in crystal oscillation circuit.
• Small number of external components for easy application.
• Wide application-wireless data equipment, MCA system.
• Low power consumption CMOS.
• Package options:
  18-pin plastic DIP (DIP18-P-300-2.54) (Product name: MSM6948-3RS)
  24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name: MSM6948-3GS-VK)


Pinout

Connection Diagram


Specifications

Parameter
Symbol
Condition
Rating
Unit
Power Supply Voltage
VDD

Ta = 25°C
with respect to AG and DG
0.3 to 7
V
Analog Input Voltage *1
VIA
0.3 to VDD + 0.3
Digital Input Voltage *2
VID
0.3 to VDD+ 0.3
Operating Temperature
TOP
-
30 to 70
°C
Storage Temperature
TSTG
-
55 to 150
*1 TI, AI
*2 ME, SD, CF, CT, FT


Description

The MSM6948-3V is a single chip MSK (Minimum Shift Keying) modem which is fabricated by Oki's low power consumption CMOS silicon gate technology.

The demodulator MSM6948-3V receives the data to be transmitted (SD) synchronized with the transmit timing clock (ST) generated by the on-chip clock generator. The signal, which is modulated by MSK method, is output.

The demodulator MSM6948-3V converts the received MSK signal to the received data (RD) by means of a delay detection technique after limiting the band of the received MSK signal. This signal is input to the digital PLL and the re-generated timing clock (RT) is output from the demodulator, synchronized with the RD.




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