MSC23V47257TD-50BS18

Here are some descriptions of the MSC23V47257TD-50BS18. The MSC23V47257TD-50BS18 is a 4,194,304-word x 72-bit CMOS dynamic random access memory module which is composed of nine 16Mb(4Mx4) DRAMs in TSOP packages mounted with nine decoupling capacitors. This is an 168-pin dual in-line memory module. This module supports any application where high density and large capacity of storage memory are required.

Here are some features of the MSC23V47257TD-50BS18. The MSC23V47257TD-50BS18 has 4,194,304-word x 72-bit organization, 168-pin Dual In-line Memory Module ,gold tab, single 3.3V power supply and ±0.3V tolerance. The input of MSC23V47257TD-50BS18 is LVTTL compatible and the output of the MSC23V47257TD-50BS18 is LVTTL compatible, 3-state, refresh is 2048cycles/ 32ms and the /CAS before /RAS refresh is hidden refresh, /RAS only refresh is capability. The fast page mode with EDO is read modify write capability and multi-bit test mode capability. Finally, the MSC23V47257TD-50BS18 has Serial Presence Detect.

Here are some ratings of MSC23V47257TD-50BS18. Firstly the maximum of access time is made up of 4 parts, t_RAC is 50ns, t_AA is 25ns, t_CAC is 13ns and t_OEA is 13ns. Secondly, the minimum of cycle time is 84bs. Finally, the maximum of power dissipation is made up of 2 parts, the operating is 6480 mW, the standby is 32.4 mW.

Here are some absolute maximum ratings of MSC23V47257TD-50BS18. The voltage on any pin relative to V_SS is -0.5 to 4.6 V, the voltage on V_CC supply relative to V_SS is -0.5 to 4.6 V, short circuit output current is 50 mA, the power dissipation is 18 W, the operating temperature is 0 to 70 °C, the storage temperature is -40 to 125 °C. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet.