Features: • 12 N-channel, 100V, 200mA, 10W, fully-floating DMOS power FETs (can be paralleled for 100V, 2.4A, 0.83W single, half-bridge, or bilateral switches)
• 40 high-voltage PMOS FETs (for level shifting, high-voltage amplifiers)
• 12 high-voltage 200W, DMOS FETs (for level shifting, voltage amplifiers)
• 20 high-voltage, grounded-source, DMOS FETs (for level shifting, current mirrors)
• >100 uncommitted CMOS gates
• 12 CMOS/TTL I/O buffers
• 13 low-voltage CMOS tile arrays (for op amps, comparators, digital circuitry)
• 14 dual-collector PNPs and 12 NPNs (for trimmed bandgaps, low-offset amplifiers or comparators, temperature sensor)
• 3-bit trimming network (for production trimmed bandgaps or offsets)
• High- and low-value resistors and capacitors (>1MW total resistance, 45pF total capacitance)
• 12V and 6V zener diodes (gate-to-source clamps, voltage references)
• 67 I/O pads (36 include 2kV ESD protection)
• Guaranteed 55°C to +150°C operation
• Several package options
• Low-cost prototyping program
• Design support via InternetApplication• 2 and 3 motor control
• High-voltage, controlled-slew, bus drivers
• High-voltage display drivers
• Lamp drivers with current limit and overtemperature protection
• Relay and solenoid drivers
• Half- and full-bridge drivers
• Multioutput switching power supplies
• High-voltage linear power supplies
• High-voltage signal processingSpecificationsDC Input Voltage
Negative, Any Pin (VIL), Note 1 ....................... VSUB 0.5V
DC Input Voltage
Positive ESD Pin (VIH), Note 2 ...............................V+ + 0.5V
Low-Voltage Supply Differential, Note 3 .....................+16.5V
DMOS Output Device Breakdown (BVDSS), Note 4 .+110V
DMOS Drain Current
Continuous (ID(max)), Note 5 ........................................ 0.2A
Pulsed (ID(pulse)), Note 6 ............................................. 0.5A
DMOS Gate Drive Voltage (VGS(max)), Note 7 ...............±20V
Standard ESD Structure Voltage (VESD), Note 8 .............. 2kV
Storage Temperature (TS) ....................... 65°C to +150°C
General Note: Devices are ESD protected; however, handling precautions are recommended.
Note 1: VSUB is the substrate bias voltage.
Note 2: V+ is the positive ESD clamp potential, user specificed up to +100V.
Note 3: Maximum voltage across low-voltage analog or digital MOS.
Note 4: DMOS source-to-body shorted to substrate at 0V.
Note 5: VGS = 15V.
Note 6: 5ms pulse, 10% duty cycle.
Note 7: Measured relative to source-to-body short.
Note 8: Measured between any two pins.
DescriptionThe MPD8021 is a semicustom, high-voltage, mixed-mode, power ASIC (Application Specific Integrated Circuit) suitable for quantities from 10 to 100,000's of pieces. Clients can begin designing proprietary ASICs using a low-cost SPICE simulator and the free MPD8021 Design Kit-available for downloading via the Internet.
Technology
The MPD8021 features bipolar/CMOS/DMOS high-voltage technology and is fabricated using Micrel's proprietary BCD5 process to combine high-speed, low-voltage digital and analog circuits with high-voltage DMOS power drive circuits on a single chip.
All logic and analog circuitry is powered from a single +3V to +12V supply. The high-voltage portion functions at oltages from +20V to over +100V and includes a charge pump.
Rapid Turnaround
Micrel delivers rapid turnaround by applying a unique metal interconnect pattern, based on the client's design, to a stock MPD8021 wafer. To facilitate a rapid and low-cost design approach, Micrel offers MPD8021 development programs that range from limited assistance to full turnkey.
When you are ready for production, count on Micrel's proven fab and test group to provide timely deliveries of high-quality, fully-tested, proprietary ICs.
Low-Cost Development
There is no cost or obligation to begin developing your own MPD8021-based custom IC. "Kit parts" which are actual working designs, featuring access to many internal functions, are available for breadboarding circuits.
MPD8021 Data Sheet
