MPC9990

* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolutemaximumrated conditions is not implied.

The MPC9990 is a low voltage PLL clock driver designed for high speed clock generation and distribution in high performance computer, workstation and server applications. The clock driver accepts a LVPECL compatible clock signal and provides 10 low skew, differential HSTL1 compatible outputs, one HSTL compatible output for system synchronization purposes and one HSTL compatible PLL feedback output. The MPC9990 operates from a dual voltage supply: 3.3 V for the core logic and 1.8 V for the HSTL outputs. The fully integrated PLL supports an input frequency range of 75 to 287.5 MHz. The output frequencies are configurable.
• Supports high performance HSTL clock distribution systems
• Compatible to IA64 processor systems
• Fully Integrated PLL, differential design
• Core logic operates from 3.3 V power supply
• HSTL outputs operate from a 1.8 V supply
• Programmable frequency by output bank
• 10 HSTL compatible outputs (two banks)
• HSTL compatible PLL feedback output
• HSTL compatible sychronization output (QSYNC)
• Max. skew of 80 ps within output bank
• Zerodelay capability: max. SPO (tpd) window of 150 ps
• LVPECL compatible clock input, LVCMOS compatible control inputs
• Temperature range of 0 to +70
The MPC9990 provides output clock frequencies required for highperformance computer system optimization. The device drives up to 10 differential clock loads within the frequency range of 75 to 287.5 MHz. The 10 outputs are organized in 2 banks of 3 and 7 differential outputs. In the standard configuration the QFB output pair is connected to the FB input pair closing the PLL loop and enabling zero delay operation from the CLK input to the outputs. Bank B outputs are frequency and phase aligned to the CLK input, providing exact copies of the highspeed input signal. Bank A outputs are configured to operate at slower speeds driving the system bus devices. The output frequency ratio of bank A to bank B is adjustable (for available ratios, see "MPC9990 Application: CPU to System Bus Frequency Ratios" on page 2) for system optimization. In a computer application, bank B outputs generate the clock signals for the devices operating at the CPU frequency, while Bank A outputs are configured to drive the clock signals for the MPC9990 running at lower speeds (system clock). Four individual frequency ratios are available, providing a high degree of flexibility. The frequency ratios between CPU clock and system clock provided by the MPC9990 are listed in the table "Output configuration" on page 4.

The QSYNC output functionality of MPC9990 is designed for system synchronization purpose. QSYNC is asserted at coincident rising edges of CPU (bank B and QFB signal) and slower system clock (bank A) outputs (see "QSYNC Phase Relation Diagram" on page 4), providing baseline timing in systems with fractional clocks. The QSYNC output is asserted for one QFB high pulse, centered on the rising QFB output.