Features: • 8 LVCMOS outputs for processor and other circuitry
• 2 differential LVDS outputs for Rapid I/O interface
• Crystal oscillator or external reference input
• 25 or 33 MHz Input reference frequency
• Selectable output frequencies include = 200, 166, 133,125, 111, 100, 83, 66, 50, 33 or 16 MHz
• Buffered reference clock output
• Rapid I/O (LVDS) Output = 500, 250 or 125 MHz
• Low cycle-to-cycle and period jitter
• 100 lead PBGA package
• 3.3V supply with 3.3V or 2.5V (Bank B) output LVCMOS drive
• Supports computing, networking, telecommunications applications
• Ambient temperature range 40 to +85Specifications
| Symbol |
Characteristics |
Min |
Max |
Unit |
Condition |
| VDD |
Supply Voltage (core) |
-0.3 |
3.8 |
V |
|
| VDDC |
Supply Voltage (Analog Supply Voltage) |
-0.3 |
VDD |
V |
|
| VDDOB |
Supply Voltage (LVCMOS output for Bank B) |
-0.3 |
VDD |
V |
|
| VIN |
DC Input Voltage |
-0.3 |
VDD+0.3 |
V |
|
| VOUT |
DC Output Voltage |
-0.3 |
VDDx+0.3 |
V |
|
| IIN |
DC Input Current |
|
±20 |
mA |
|
| IOUT |
DC Output Current |
|
±50 |
mA |
|
| TS |
Storage Temperature |
-65 |
125 |
|
|
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied.
b. VDDx references power supply pin associated with specific output pin.
DescriptionThe MPC9850 uses either a 25 or 33 MHz reference frequency to generate 8 LVCMOS output clocks, of which, the frequency is selectable from 16 MHz to 200 MHz. The reference is applied to the input of a PLL and multiplied to 2 GHz. Output dividers, divide this frequency by 10, 12, 15, 16, 18, 20, 24, 30, 40, 60 or 120 to produce output frequencies of 200, 166, 133, 125, 111, 100, 83 66 50 33 or 16 MHz. The single-ended LVCMOS outputs are divided into two banks of 4 low skew outputs each, for use in driving a microprocessor or microcontroller clock input as well as other system components. The 2 GHz PLL output frequency is also divided to produce a 125, 250 or 500 MHz clock output for Rapid I/O applications such as found on the PowerQUICC III communications processor. The input reference, either crystal or external input MPC9850 is also buffered to a separate output that my be used as the clock source for a Gigabit Ethernet PHY if desired.
The reference clock of MPC9850 may be provided by either an external clock input of 25 MHz or 33 MHz. An internal oscillator requiring a 25 MHz crystal for frequency control may also be used. The external clock source my be applied to either of two clock inputs and selected via the CLK_SEL control input. Both single ended LVCMOS and differential LVPECL inputs are available. The crystal oscillator or external clock input is selected via the input pin of REF_SEL. Other than the crystal, no external components are required for crystal oscillator operation. The REF_33MHz configuration pins is used to select between a 33 and 25 MHz input frequency.
The MPC9850 is packaged in a 100 lead MAPBGA package to optimize both performance and board density.
MPC9850 Data Sheet
