MPC9653A

Programming the MPC9653A
The MPC9653A supports output clock frequencies from 25 to 125 MHz. Two different feedback divider configurations can be used to achieve the desired frequency operation range. The feedback divider (VCO_SEL) should be used to situate the VCO in the frequency lock range between 200 and 500 MHz for stable and optimal operation. Two operating frequency ranges are supported: 25 to 62.5 MHz and 50 to 125 MHz. Table 7 illustrates the configurations supported by the MPC9653A. PLL zero-delay is supported if BYPASS = 1, PLL_EN = 1 and the input frequency is within the specified PLL reference frequency range.

The MPC9653A utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC9653A requires the connection  of the QFB output to the feedback input to close the PLL feedback path (external feedback). With the PLL locked, the output frequency is equal to the reference frequency of the device and VCO_SEL selects the operating frequency range of 25 to 62.5 MHz or 50 to 125 MHz. The two available post-PLL dividers selected by VCO_SEL (divide-by-4 or divide-by-8) and the reference clock frequency determine the VCO frequency. Both must be selected to match the VCO frequency range. The internal VCO of the MPC9653A is running at either 4x or 8x of the reference clock frequency. The MPC9653A is guaranteed to lock in a low power PLL mode in the high frequency range (VCO_SEL = 0) down to PLL = 145 MHz or Fref = 36.25 MHz.

The MPC9653A has a differential LVPECL reference input along with an external feedback input. The device is ideal for use as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance.

The PLL_EN and BYPASS controls select the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock of MPC9653A is bypassing the PLL and routed either to the output dividers or directly to the outputs. The PLL bypass configurations are fully static and the minimum clock frequency specification and all other PLL characteristics do not apply.

The outputs of MPC9653A can be disabled (high-impedance) and the device reset by asserting the MR/OE pin. Asserting MR/OE also causes the PLL to loose lock due to missing feedback signal presence at FB_IN. Deasserting MR/OE will enable the outputs and close the phase locked loop, enabling the PLL to recover to normal operation.

The MPC9653A is fully 3.3 V compatible and requires no external loop filter components. The inputs (except PCLK) accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC9653A outputs can drive one or two traces giving the devices an effective fanout of 1:16. The device is packaged in a 7x7 mm2 32-lead LQFP package.