MPC9653

·The MPC9653 supports output clock frequencies from 25 to 125 MHz. Two different feedback divider configurations can be used to achieve the desired frequency operation range. The feedback divider (VCO_SEL) should be used to situate the VCO in the frequency lock range between 200 and 500 MHz for stable and optimal operation. Two operating frequency ranges are supported: 25 to 62.5 MHz and 50 to 125 MHz. Table 9 illustrates the configurations supported by the MPC9653. PLL zero-delay is supported if BYPASS=1, PLL_EN=1 and the input frequency is within the specified PLL reference frequency range.

The MPC9653 is a 3.3V compatible, 1:8 PLL based clock generator and zero-delay buffer targeted for high performance low-skew clock distribution in mid-range to high-performance telecom, networking and computing applications. With output frequencies up to 125 MHz and output skews less than 150 ps the MPC9653 meets the needs of the most demanding clock applications.