MPC961

* Absolute maximum continuos ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied.

The MPC961 is a 2.5V or 3.3V compatible, 1:18 PLL based zero delay buffer. With output frequencies of up to 200MHz, output skews of 150ps the device meets the needs of the most demanding clock tree applications.
• Fully Integrated PLL
• Up to 200MHz I/O Frequency
• LVCMOS Outputs
• Outputs Disable in High Impedance
• LVPECL Reference Clock Options
• LQFP Packaging
• ±50ps CycleCycle Jitter
• 150ps Output Skews
The MPC961 is offered with two different input configurations. The MPC961C offers an LVCMOS reference clock while the MPC961P offers  an LVPECL reference clock.

When pulled high the OE pin MPC961 will force all of the outputs (except QFB) into a high impedance state. Because the OE pin does not affect the QFB output, down stream clocks can be disabled without the internal PLL losing lock.

The MPC961 is fully 2.5V or 3.3V compatible and requires no external loop filter components. All control inputs accept LVCMOS compatible levels and the outputs provide low impedance LVCMOS outputs capable of driving terminated 50
transmission lines. For series terminated lines the MPC961 can drive two lines per output giving the device an effective fanout of 1:36. The device is packaged in a 32 lead LQFP package to provide the optimum combination of board density and performance.