MPC958

* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolutemaximumrated conditions is not implied.

The MPC958 is a 3.3V compatible, PLL based clock driver device targeted for high performance clock tree designs. With output frequencies of up to 200MHz and output skews of 200ps the MPC958 is ideal for the most demanding clock tree designs. The devices employ a fully differential PLL design to minimize cycletocycle and phase jitter.
• Fully Integrated PLL
• Output Frequency up to 200MHz
• Outputs Disable in High Impedance
• LQFP Packaging
• 100ps CycletoCycle Jitter
The MPC958 has a differential LVPECL reference input along with an external feedback input. These features make the MPC958 ideal for use as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance. The MR/OE input pin will tristate the output buffers when driven "high".

The MPC958 is fully 3.3V compatible and requires no external loop filter components. All control inputs accept LVCMOS or LVTTL compatible levels while the outputs provide LVCMOS levels with the ability to drive terminated 50W transmission lines. For series terminated 50W lines, each of the MPC958 outputs can drive two traces giving the device an effective fanout of 1:22. The device is packaged in a 7x7mm 32lead LQFP package to provide the optimum combination of board density and performance.