MPC954

* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolutemaximumrated conditions is not implied.

The MPC954 is a 3.3V compatible, PLL based zero delay buffer targeted for high performance clock tree designs. With 11 outputs at frequencies of up to 100MHz and output skews of 200ps the MPC954 is ideal for the most demanding clock tree designs. The devices employ a fully differential PLL design to minimize cycletocycle and phase jitter.
• Fully Integrated PLL
• Output Frequency up to 100MHz
• Outputs Disable in High Impedance
• TSSOP Packaging
• 50ps CycletoCycle Jitter Typical
The analog V_CC pin of the MPC954 also serves as a PLL bypass select pin. When driven low the V_CCA pin will route the REF_CLK input around the PLL directly to the outputs. The OE input is a logic enable for all of the outputs except QFB. A low on the OE pin forces Q0Q9 to a logic low state.

The MPC954 is fully 3.3V compatible and requires no external loop filter components. All inputs accept LVCMOS or LVTTL compatible levels while the outputs provide LVCMOS levels with the ability to drive terminated 50W transmission lines. The output impedance of it is 10, therefore for series terminated 50W lines, each of the MPC954 outputs can drive two traces giving the device an effective fanout of 1:22.

The MPC954 is packaged in a 24lead TSSOP package to provide the optimum combination of board density and performance.