MPC9446

Features: • Configurable 10 outputs LVCMOS clock distribution buffer• Compatible to single, dual and mixed 3.3V/2.5V voltage supply• Wide range output clock frequency up to 250 MHz• Designed for mid-range to high-performance telecom, networking andcomputer applications̶...

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MPC9446 Picture
SeekIC No. : 004426165 Detail

MPC9446: Features: • Configurable 10 outputs LVCMOS clock distribution buffer• Compatible to single, dual and mixed 3.3V/2.5V voltage supply• Wide range output clock frequency up to 250 MHz...

floor Price/Ceiling Price

Part Number:
MPC9446
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/26

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Product Details

Description



Features:

• Configurable 10 outputs LVCMOS clock distribution buffer
• Compatible to single, dual and mixed 3.3V/2.5V voltage supply
• Wide range output clock frequency up to 250 MHz
• Designed for mid-range to high-performance telecom, networking andcomputer applications
• Supports applications requiring clock redundancy
• Max. output skew of 200 ps (150 ps within one bank)
• Selectable output configurations per output bank
• Tristable outputs
• 32 ld LQFP package
• Ambient operating temperature range of -40 to 85°C



Specifications

Symbol Characteristics Min Max Unit Condition
VCC Supply Voltage -0.3 -3.6 V  
VIN DC Input Voltage -0.3 VCC+0.3 V  
VOUT DC Output Voltage -0.3 VCC+0.3 V  
IIN DC Input Current   ±20 ma  
IOUT DC Output Current   ±50 ma  
TS Storage temperature 65 125    



Description

The MPC9446 is a full static fanout buffer design supporting clock frequencies up to 250 MHz. The signals are generated and retimed on-chip to ensure minimal skew between the three output banks. Two independent LVCMOS compatible clock inputs are available. MPC9446 feature supports redundant clock sources or the addition of a test clock into thesystem design. Each of the three output banks can be individually supplied by 2.5V or 3.3V supporting mixed voltage applications. The FSELx pins choose between division of the input reference frequency by one or two. The frequency divider can be set individually for each of the three output banks. The MPC9446 can be reset and the outputs are disabled by deasserting the MR/OE pin (logic high state). Asserting /OE will enable the outputs.

All inputs accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. Please consult the MPC9456 specification for a 1:10 mixed voltage buffer with LVPECL compatible inputs. For series terminated transmission lines, each of the MPC9446 outputs can drive one or two traces giving the devices an effective fanout of 1:20. The MPC9446 is packaged in a 7x7 mm2 32-lead LQFP package.


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