MPC940L

* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolutemaximumrated conditions is not implied.

The MPC940L is a 1:18 low voltage clock distribution chip with 2.5V or 3.3V LVCMOS output capabilities. The MPC940L features the capability to select either a differential LVPECL or an LVCMOS compatible input. The 18 outputs are 2.5V or 3.3V LVCMOS compatible and feature the drive strength to drive 50 series or parallel terminated transmission lines.

With outputtooutput skews of 150ps, the MPC940L is ideal as a clock distribution chip for the most demanding of synchronous systems. The 2.5V outputs also make the MPC940L ideal for supplying clocks for a high performance microprocessor based design. For a similar device at a lower price/performance point the reader is referred to the MPC9109.
• LVPECL or LVCMOS Clock Input
• 2.5V LVCMOS Outputs for Pentium II Microprocessor Support
• 150ps Maximum OutputtoOutput Skew
• Maximum Output Frequency of 250MHz
• 32Lead LQFP Packaging
• Dual or Single Supply Device:
• Dual VCC Supply Voltage, 3.3V Core and 2.5V Output
• Single 3.3V VCC Supply Voltage for 3.3V Outputs
• Single 2.5V VCC Supply Voltage for 2.5V I/O
With a low output impedance (920W), in both the HIGH and LOW logic states, the output buffers of the MPC940L are ideal for driving series terminated transmission lines. With a 20W output impedance the 940L has the capability of driving two series terminated lines from each output.

MPC940L gives the device an effective fanout of 1:36. If a lower output impedance is desired please see the MPC942 data sheet.

The differential LVPECL inputs of the MPC940L allow the MPC940L to interface directly with a LVPECL fanout buffer like the MC100EP111 to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS input provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In addition, the two clock sources can be used to provide for a test clock interface as well as the primary system clock. A logic HIGH on the LVCMOS_CLK_Sel pin will select the LVCMOS level clock input. All inputs of the MPC940L have internal pullup/pulldown resistor so they can be left open if unused.

The MPC940L is a single or dual supply device. The device power supply offers a high degree of flexibility. The MPC940L can operate with a 3.3V core and 3.3V output, a 3.3V core and 2.5V outputs as well as a 2.5V core and 2.5V outputs. The 32lead LQFP package was chosen to optimize performance, board space and cost of the device. The 32lead LQFP has a 7x7mm body size with a conservative 0.8mm pin spacing.