Features: • 1:6 PLL based low-voltage clock generator
• 3.3V power supply
• Generates clock signals up to 120 MHz
• Maximum output skew of 150 ps
• On-chip crystal oscillator clock reference
• Alternative LVCMOS PLL reference clock input
• Internal and external PLL feedback
• PLL multiplies the reference clock by 4x, 3x, 2x, 1x, 4/3x, 3/2x, 2/3x, x/2, x/3 or x/4
• Supports zero-delay operation in external feedback mode
• Synchronous output clock stop in logic low eliminates output runt pulses
• Power_down feature reduces output clock frequency
• Drives up to 12 clock lines
• 32 lead LQFP packaging
• Ambient temperature range 0 to +70
• Internal PowerUp Reset
• Pin and function compatible to the MPC930Pinout
Specifications
| Symbol |
Characteristics |
Min |
Max |
Unit |
Condition |
| VCC |
Supply Voltage |
-0.3 |
3.9 |
V |
|
| VIN |
DC Input Voltage |
-0.3 |
VCC+0.3 |
V |
|
| VOUT |
DC Output Voltage |
-0.3 |
VCC+0.3 |
V |
|
| IIN |
DC Input Current |
|
±20 |
mA |
|
| IOUT |
DC Output Current |
|
±50 |
mA |
|
| TS |
Storage Temperature |
-65 |
125 |
|
|
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied.
DescriptionThe MPC9330 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC9330 requires either the selection of internal PLL feedback or the connection of one of the device outputs to the feedback input to close the PLL feedback path in external feedback mode. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. In external PLL feedback configuration and with the available post-PLL dividers (divide-by-2, divide-by-4 and divide-by-6), the internal VCO of the MPC9330 is running at either 4x, 8x, 12x, 16x or 24x of the reference clock frequency. In internal feedback configuration (divide-by-16) the internal VCO is running 16x of the reference frequency. The frequency of the QA, QB, QC output banks is a division of the VCO frequency and can be configured independently for each output bank using the FSELA, FSELB and FSELC pins, respectively. The available output to input frequency ratios are 4x, 3x, 2x, 1x, 4/3x, 3/2x, 2/3x, x/2, x/3 or x/4.
The REF_SEL pin of MPC9330 selects the internal crystal oscillator or the LVCMOS compatible input as the reference clock signal.
The PLL_EN MPC9330 control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The PLL MPC9330 bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply.
The outputs of MPC9330 can be disabled (high-impedance) by deasserting the OE/MR pin. In the PLL configuration with external feedback selected, deasserting OE/MR causes the PLL to loose lock due to missing feedback signal presence at FB_IN. Asserting OE/MR will enable the outputs and close the phase locked loop, enabling the PLL to recover to normal operation. The MPC9330 output clock stop control allows the outputs to start and stop synchronously in the logic low state, without the potential generation of runt pulses.
The MPC9330 is fully 3.3V compatible and requires no external loop filter components. All inputs (except XTAL) accept
LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC9330 outputs can drive one or two traces giving the devices an effective fanout of 1:12. The device is packaged in a 7x7 mm2 32-lead LQFP package.
MPC9330 Data Sheet
