MPC601

The 601 is a high-performance, superscalar PowerPC implementation. The PowerPC architecture allows optimizing compilers to schedule instructions to maximize performance through efficient use of the PowerPC instruction set and register model. The multiple, independent execution units allow compilers to maximize parallelism and instruction throughput. Compilers that take advantage of the flexibility of the PowerPC architecture can additionally optimize system performance of the PowerPC processors.

The 601 implements the PowerPC architecture, with the extensions and variances listed in Appendix H, "Implementation Summary for Programmers," in the PowerPC 601 RISC Microprocessor User's Manual.

Specific features of the 601 are listed in Section 1.1, "PowerPC 601 Microprocessor Features."