MMC2080

The MMC2080/2075 offers the following suite of features.

• M•CORE™ RISC Processor

- 32-bit load/store M•CORE RISC architecture
- Fixed 16-bit instruction length
- 16-entry 32-bit general-purpose register file
- 32-bit internal address and data buses
- Efficient, four-stage, fully interlocked execution pipeline
- Single-cycle execution for most instructions; two cycles for branches and memory accesses
- Special branch, byte, and bit manipulation instructions
- Support for byte, halfword, and word memory accesses
- Fast interrupt support via vectoring/auto-vectoring and a 16-entry dedicated alternate register file

• Integrated Roaming FLEX alphanumeric decoder (MMC2080 only)

- FLEX paging protocol signal processor
- 1600, 3200, and 6400 bits per second (bps) decoding
- Highly programmable receiver control
- FLEX message fragmentation and group messaging support
- SSID and NID roaming support
- Internal demodulator and data slicer
- Improved battery savings via partial address correlation and intermittent receiver clock
- Full support for revision G1.9 of the FLEX protocol
- External CAP code access through parallel or serial FLASH/PROM

• On-chip memory

- 24 K * 32 CPU ROM (96 K)
- 1.5 K * 32 CPU RAM (6 K)

• On-chip peripherals

- Asynchronous serial communications interface (SCI) with IrDA capability
- Synchronous serial peripheral interface (SPI)
- Frequency synthesizer controller (FSC)
- Melody generator
- 4 * 4 keypad interface
- Multipurpose I/O ports (MPIO)
- Two 16-bit general purpose timers
- Time-of-day (TOD) timer
- Watchdog timer
- Vectored interrupt controller with 16 programmable priority levels
- Oscillator and PLL with software selectable speeds
- AMBA peripheral bridge depipelines system bus for simpler peripheral bus
- 8/16-bit external system bus with 22-bit address bus

• Operating features

- Processor operation to 10 MHz over full operating range
- Low-power modes
- OnCE™ (On-Chip Emulation) debug module
- Voltage range 1.8 V to 3.6 V; temperature range -20 °C to 85 °C
- Chip-select outputs for four external devices (4 Mbyte per chip select, 16 Mbyte directly addressable)
- Programmable wait states for external accesses
- External boot option
- External bus interface that accepts internal, half-word, and byte transfers
- External device that may become system bus master

• Development tools

- Development option (different package) that adds select to bypass internal ROM
- Development option (different package) that extends external bus to 32 bits
- External bus that can display internal transfers