Features: Typical propagation delay: 13 ns Wide power supply range: 2±6V Low quiescent current: 80 mA maximum (74 HC) TRI-STATE outputs for connection to bus oriented systems High output drive: 6 mA (min)Specifications Supply Voltage (VCC)DC Input Voltage (VIN)DC Output Voltage (VOUT)Clamp...
MM74HC643: Features: Typical propagation delay: 13 ns Wide power supply range: 2±6V Low quiescent current: 80 mA maximum (74 HC) TRI-STATE outputs for connection to bus oriented systems High output drive: 6 m...
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Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temp. (TL) (Soldering 10 seconds) |
-0.5 to +7.0V -1.5 to VCC+1.5V -0.5 to VCC+0.5V ±20 mA ±25 mA ±50 mA -65oC to +150oC 600 mW 500 mW 260oC |
These TRI-STATE bi-directional buffers MM74HC643 utilize advanced silicon- gate CMOS technology, and are intended for two-way asynchronous communication between data buses. They have high drive current outputs which enable high speed operation even when driving large bus capacitances. These circuits MM74HC643 possess the low power consumption and high noise immunity usually associated with CMOS circuitry, yet have speeds comparable to low power Schottky TTL circuits.
MM74HC643 has an active low enable G and a direction control input, DIR. When DIR is high, data flows from the A inputs to the B outputs. When DIR is low, data flows from the B inputs to the A outputs. The MM54HC640/ MM74HC640 transfers inverted data from one bus to other and the MM54HC643/MM74HC643 transfers inverted data from the A bus to the B bus and true data from the B bus to the A bus.
These MM74HC643 can drive up to 15 LS-TTL Loads, and all inputs are protected from damage due to static discharge by diodes to VCC and ground.