Features: Typical operating frequency: 45 MHz Typical propagation delay: ns (clock to Q) Wide operating supply voltage range: 2±6V Low input current: 1 mA maximum Low quiescent supply current: 160 mA maximum (74HC Series) Fanout of 10 LS-TTL loadsSpecifications Supply Voltage (VCC)DC Input...
MM74HC194: Features: Typical operating frequency: 45 MHz Typical propagation delay: ns (clock to Q) Wide operating supply voltage range: 2±6V Low input current: 1 mA maximum Low quiescent supply current: 160 ...
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Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temp. (TL) (Soldering 10 seconds) |
-0.5 to +7.0V -1.5 to VCC+1.5V -0.5 to VCC+0.5V ±20 mA ±25 mA ±50 mA -65oC to a150oC 600 mW 500 mW 260oC |
This 4-bit high speed bidirectional shift register MM74HC194 utilizes advanced silicon-gate CMOS technology to achieve the low power consumption and high noise immunity of standard CMOS integrated circuits, along with the ability to drive 10 LS-TTL loads. This MM74HC194 operates at speeds similar to the equivalent low power Schottky part.
This bidirectional shift register MM74HC194 is designed to incorporate virtually all of the features a system designer may want in a shift register. It features parallel inputs, parallel outputs, right shift and left shift serial inputs, operating mode control inputs, and a direct overriding clear line. The register MM74HC194 has four distinct modes of operation: PARALLEL (broadside) LOAD; SHIFT RIGHT (in the direction QA toward QD); SHIFT LEFT; INHIBIT CLOCK (do nothing).
Synchronous parallel loading of MM74HC194 is accomplished by applying the four bits of data and taking both mode control inputs, S0 and S1, high. The data are loaded into their respective flip flops and appear at the outputs after the positive transition of the CLOCK input. During loading, serial data flow of MM74HC194 is inhibited. Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial data for this mode is entered at the SHIFT RIGHT data input. When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the SHIFT LEFT serial input. Clocking of the flip flops is inhibited when both mode control inputs are low. The mode control inputs of MM74HC194 should be changed only when the CLOCK input is high.
The MM74HC194 is functionally as well as pinout compatible with the standard 54LS/74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.