MM74HC165

Features: Typical propagation delay: 20 ns (clock to Q)Wide operating supply voltage range: 26VLow input current: 1 uA maximumLow quiescent supply current: 80 mA maximum (74HCSeries)Fanout of 10 LS-TTL loadsSpecificationsSupply Voltage (VCC) -0.5 to +7.0VDC Input Voltage (VIN) -1.5 to VCC +1.5VDC ...

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SeekIC No. : 004423064 Detail

MM74HC165: Features: Typical propagation delay: 20 ns (clock to Q)Wide operating supply voltage range: 26VLow input current: 1 uA maximumLow quiescent supply current: 80 mA maximum (74HCSeries)Fanout of 10 LS-...

floor Price/Ceiling Price

Part Number:
MM74HC165
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/26

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Product Details

Description



Features:

 Typical propagation delay: 20 ns (clock to Q)
 Wide operating supply voltage range: 26V
 Low input current: 1 uA maximum
 Low quiescent supply current: 80 mA maximum (74HCSeries)
 Fanout of 10 LS-TTL loads



Specifications

Supply Voltage (VCC)                                 -0.5 to +7.0V
DC Input Voltage (VIN)                       -1.5 to VCC +1.5V
DC Output Voltage (VOUT)                  -0.5 to VCC +0.5V
Clamp Diode Current (IIK, IOK)                           ±20 mA
DC Output Current, per pin (IOUT)                      ±25 mA
DC VCC or GND Current, per pin (ICC)                 ±50 mA
Storage Temperature Range (TSTG)         -65 to +150
Power Dissipation (PD)
(Note 3)                                                               600 mW
S.O. Package only                                               500 mW
Lead Temperature (TL)
(Soldering 10 seconds)                                           260



Description

The MM74HC165 high speed PARALLEL-IN/SERIAL-OUTSHIFT REGISTER utilizes advanced silicon-gate CMOS technology. It has the low power consumption and highnoise immunity of standard CMOS integrated circuits,along with the ability to drive 10 LS-TTL loads.
This 8-bit serial shift register of MM74HC165 shifts data from QA to QHwhen clocked. Parallel inputs to each stage are enabled bya low level at the SHIFT/LOAD input. Also included is agated CLOCK input and a complementary output from theeighth bit.
Clocking is accomplished through a 2-input NOR gate permittingone input to be used as a CLOCK INHIBIT function.Holding either of the CLOCK of MM74HC165 inputs high inhibits clocking,and holding either CLOCK input low with the SHIFT/LOADinput high enables the other CLOCK input. Data transferoccurs on the positive going edge of the clock. Parallelloading is inhibited as long as the SHIFT/LOAD input isHIGH. When taken LOW, data at the parallel inputs isloaded directly into the register independent of the state ofthe clock.
The MM74HC165 is functionally as well as pin-outcompatible with the standard 74LS logic family. All inputsare protected from damage due to static discharge by internaldiode clamps to VCC and ground.




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