Features: * Typical operating frequency: 40 MHz
* Typical propagation delay; clock to Q: 18 ns
* Low quiescent current: 80 mA maximum (74HC Series)
* Low input current: 1 mA maximum
* Wide power supply range: 26VSpecificationsSupply Voltage (VCC) -0.5 to +7.0V
DC Input Voltage (VIN) -1.5 to VCC+1.5V
DC Output Voltage (VOUT) -0.5 to VCC+0.5V
Clamp Diode Current (IIK, IOK) ±20 mA
DC Output Current, per pin (IOUT) ±25 mA
DC VCC or GND Current, per pin (ICC) ±50 mA
Storage Temperature Range (TSTG) -65°C to +150°C
Power Dissipation (PD)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature
(TL) (Soldering 10 seconds) 260°C DescriptionThe MM74HC161 and MM74HC163 synchronous presettable counters utilize advanced silicon-gate CMOS technology and internal look-ahead carry logic for use in high speed counting applications. They offer the high noise immunity and low power consumption inherent to CMOS with speeds similar to low power Schottky TTL. The MM74HC161 are 4 bit binary counters. All flip-flops are clocked simultaneously on the LOW-to-HIGH transition (positive edge) of the CLOCK input waveform.
These counters MM74HC161 may be preset using the LOAD input. Presetting of all four flip-flops is synchronous to the rising edge of CLOCK. When LOAD is held LOW counting is disabled and the data on the A, B, C, and D inputs is loaded into the counter on the rising edge of CLOCK. If the load input of MM74HC161 is taken HIGH before the positive edge of CLOCK the count operation will be unaffected.
All of these counters MM74HC161 may be cleared by utilizing the CLEAR input. The clear function on the MM74HC163 counter is synchronous to the clock. That is, the counters are cleared on the positive edge of CLOCK while the clear input is held LOW.
The MM74HC161 counter is cleared asynchronously. When the CLEAR is taken LOW the counter is cleared immediately regardless of the CLOCK.
Two active HIGH enable inputs (ENP and ENT) and a RIPPLE CARRY (RC) output of MM74HC161 are provided to enable easy cascading of counters. Both ENABLE inputs must be HIGH to count. The ENT input also enables the RC output. When enabled, the RC outputs a positive pulse when the counter overflows. This pulse is approximately equal in duration to the HIGH level portion of the QA output. The RC output of MM74HC161 is fed to successive cascaded stages to facilitate easy implementation of N-bit counters.
All inputs of MM74HC161 are protected from damage due to static discharge by diodes to VCC and ground.
MM74HC161 Data Sheet
