Features: Typical propagation delay: 16 ns Wide operating voltage range: 2±6V Low input current: 1 mA maximum Low quiescent current: 40 mA (74HC series) High output drive: 10 LS-TTL loadsSpecifications Supply Voltage (VCC)DC Input Voltage (VIN)DC Output Voltage (VOUT)Clamp Diode Current (I...
MM74HC107: Features: Typical propagation delay: 16 ns Wide operating voltage range: 2±6V Low input current: 1 mA maximum Low quiescent current: 40 mA (74HC series) High output drive: 10 LS-TTL loadsSpecificat...
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Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temp. (TL) (Soldering 10 seconds) |
-0.5 to +7.0V -1.5 to VCC+1.5V -0.5 to VCC+0.5V ±20 mA ±25 mA ±50 mA -65oC to a150oC 600 mW 500 mW 260oC |
These J-K Flip-Flops MM74HC107 utilize advanced silicon-gate CMOS technology to achieve the high noise immunity and low power dissipation of standard CMOS integrated circuits. These devices can drive 10 LS-TTL loads.
These flip-flops MM74HC107 are edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, CLOCK, and CLEAR inputs and Q and Q outputs. CLEAR is independent of the clock and accomplished by a low level on the input.
The MM74HC107 is functionally as well as pinout compatible with the standard 54LS/74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.