Features: ` Wide supply voltage range: 3V to 15V` High noise immunity: 0.45 VCC (typ.)` Low power consumption` TTL compatibility: Fan out of 1driving standard TTL` Bus driving capability` 3-STATE outputs` Eight storage elements in one package` Single CLOCK/LATCH ENABLE and OUTPUT DISABLE control i...
MM74C373: Features: ` Wide supply voltage range: 3V to 15V` High noise immunity: 0.45 VCC (typ.)` Low power consumption` TTL compatibility: Fan out of 1driving standard TTL` Bus driving capability` 3-STATE ou...
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` Wide supply voltage range: 3V to 15V
` High noise immunity: 0.45 VCC (typ.)
` Low power consumption
` TTL compatibility: Fan out of 1driving standard TTL
` Bus driving capability
` 3-STATE outputs
` Eight storage elements in one package
` Single CLOCK/LATCH ENABLE and OUTPUT DISABLE control inputs
` 20-pin dual-in-line package with 0.300" centers takes half the board space of a 24-pin package
Voltage at Any Pin |
-0.3V to VCC + 0.3V |
Operating Temperature Range (TA) | |
MM74C373 |
-40 to +85 |
Storage Temperature Range (TS) |
-65 to +150 |
Power Dissipation | |
Dual-In-Line |
700 mW |
Small Outline |
500 mW |
Operating VCC Range |
3V to 15V |
Absolute Maximum VCC |
18V |
Lead Temperature (TL) | |
(soldering, 10 seconds) |
260 |
The MM74C373 and MM74C374 are integrated, complementary MOS (CMOS), 8-bit storage elements with 3-STATE outputs. These outputs have been specially designed to drive high capacitive loads, such as one might find when driving a bus, and to have a fan out of 1 when driving standard TTL. When a high logic level of MM74C373 is applied to the OUTPUT DISABLE input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements.
The MM74C373 is an 8-bit latch. When LATCH ENABLE is high, the Q outputs will follow the D inputs. When LATCH ENABLE goes low, data at the D inputs, which meets the set-up and hold time requirements, will be retained at the outputs until LATCH ENABLE returns high again.
The MM74C374 is an 8-bit, D-type, positive-edge triggered flip-flop. Data at the D inputs, meeting the set-up and hold time requirements, is transferred to the Q outputs on positive- going transitions of the CLOCK input.