MM74C195

· Medium speed operation 8.5 MHz (typ.) with 10V supply and 50 pF load
· High noise immunity 0.45 V_CC (typ.)
· Low power 100 nW (typ.)
· Tenth power TTL compatible Drive 2 LPTTL loads
· Supply voltage range 3V to 15V
· Synchronous parallel load
· Parallel inputs and outputs from each flip-flop
· Direct overriding clear
· J and K inputs to first stage
· Complementary outputs from last stage
· Positive-edge triggered clocking
Y Diode clamped inputs to protect against static charge

· Automotive
· Data terminals
· Instrumentation
· Medical electronics
· Alarm systems
· Remote metering
· Industrial electronics
· Computers

The MM54C195/MM74C195 CMOS 4-bit registers feature parallel inputs, parallel outputs, J-K serial inputs, shift/load control input and a direct overriding clear. The following two modes of operation are possible: Parallel Load Shift in direction QA towards QD Parallel loading is accomplished by applying the four bits of data and taking the shift/load control of input low. 

The data of MM74C195 is loaded into the associated flip-flops and appears at the outputs after the positive transition of the clock input. During parallel loading, serial data flow is inhibited.

Serial shifting of MM74C195 is accomplished synchronously when the shift/load control input is high. Serial data for this mode is entered at the J-K inputs. These inputs of MM74C195 allow the first stage to perform as a J-K, D, or T-type flip flop as shown in the truth table.