Features: ·5.0V ±10% single supply operation·Internal reference voltage·Power dissipation less than 200mW typical·Replaces TMC1175MC20 and AD775JR, functionally compatible to Sony CXD1175AM/AP·16-pin reduced pin count packages available: ML6401CS-3·Low input capacitance track and hold: 4pF·Onboard...
ML6401: Features: ·5.0V ±10% single supply operation·Internal reference voltage·Power dissipation less than 200mW typical·Replaces TMC1175MC20 and AD775JR, functionally compatible to Sony CXD1175AM/AP·16-pi...
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·5.0V ±10% single supply operation
·Internal reference voltage
·Power dissipation less than 200mW typical
·Replaces TMC1175MC20 and AD775JR, functionally compatible to Sony CXD1175AM/AP
·16-pin reduced pin count packages available: ML6401CS-3
·Low input capacitance track and hold: 4pF
·Onboard non-overlapping clock generation to minimize external components
·Three-state outputs and no missing codes
·150MHz input track and hold
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied.
Supply Current (ICC) ............................................... 55mA
Peak Driver Output Current ............................... ±500mA
Analog Inputs ................................................... 0.3 to 7V
Junction Temperature ............................................. 150°C
Storage Temperature Range ..................... 65°C to 150°C
Lead Temperature (soldering, 10 sec) ..................... 150°C
Thermal Resistance (qJA)
Plastic DIP ....................................................... 80°C/W
Plastic SOIC ...................................................110°C/W
The ML6401 is a single-chip 8-bit 20 MSPS BiCMOS Video A/D Converter IC, incorporating a differential input track and hold, clock generation circuitry, and reference voltage.
The input track and hold of ML6401 consists of a low (4pF) capacitance input and a fast settling operational amplifier. The A/D conversion is accomplished through a pipeline approach, reducing the number of required comparators and latches. The non-over-lapping clocks of ML6401 required for this architecture are all internally generated. Clock generation circuitry requires only one 50% duty cycle clock input. The use of error correction throughout the A/D converter improves DNL. All bias voltages and currents required by the A/D converter are internally generated. The digital outputs of ML6401 are three-stateable.