MK2069-04

Features: • Input clock frequency <1kHz to 170MHz• Output clock frequency of 500kHz to 160MHz• Clock translation examples: T1 (1.544MHz) to/from E1 (2.048MHz) T3 (44.736MHz) to/from E3 (34.368MHz) OC-3 (155.52MHz) to/from T1 (1.544 MHz) CCIR-601 (27MHz) to/from SMPTE 274M(74.1...

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MK2069-04 Picture
SeekIC No. : 004421681 Detail

MK2069-04: Features: • Input clock frequency <1kHz to 170MHz• Output clock frequency of 500kHz to 160MHz• Clock translation examples: T1 (1.544MHz) to/from E1 (2.048MHz) T3 (44.736MHz) to/...

floor Price/Ceiling Price

Part Number:
MK2069-04
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/26

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Product Details

Description



Features:

• Input clock frequency <1kHz to 170MHz
• Output clock frequency of 500kHz to 160MHz
• Clock translation examples:
   T1 (1.544MHz) to/from E1 (2.048MHz)
   T3 (44.736MHz) to/from E3 (34.368MHz)
   OC-3 (155.52MHz) to/from T1 (1.544 MHz)
   CCIR-601 (27MHz) to/from SMPTE 274M
(74.125MHz)
• Jitter attenuation of input clock provided by VCXO
   circuit. Jitter transfer characteristics user configured
   through external loop filter component selection.
• Low jitter and phase noise generation.
• PLL lock status output
• PLL Clear function allows seamless synchronizing to
   an altered input clock phase
• 2nd PLL provides frequency translation of VCXO
   PLL output (VCLK) to a higher or alternate output
   frequency (TCLK).
• Device will free-run in the absence of an input clock
   based on VCXO frequency.
• 56 pin TSSOP package
• Single 3.3V power supply
• 5V tolerant clock input



Pinout

  Connection Diagram


Specifications

Item Rating
Supply Voltage, VDD 7V
All Inputs and Outputs -0.5V to VDD+0.5V
Ambient Operating Temperature -40°C to +85°C
Storage Temperature -65 to +150°C
Junction Temperature 175°C
Soldering Temperature 260°C



Description

The MK2069-04 is a VCXO (Voltage Controlled Crystal Oscillator) based clock generator that features a PLL (Phase-Locked Loop) input reference divider and feedback divider that have a wide numeric range selectable by the user. This enables a complex PLL multiplication ratio that can be used for translation between clock frequency standards.

The on-chip VCXO produces a stable, low jitter output clock using a phase detector frequency down to 8 kHz or lower. This means the MK2069-04 can translate between clock frequencies that have a low common denominator, such as the 8 kHz frame clock common with telecom standards. The MK2069-04 also provides jitter attenuation of the input clock and can accept a low input frequency as well.

The device is optimized for user configurability by providing access to all major PLL divider functions. No power-up programming is needed as configuration is= pin selected. External VCXO loop filter components provide an additional level of user configurability.

The MK2069-04 includes a lock detector (LD) output that serves as a clock status monitor. The clear (CLR) input enables rapid synchronization to the phase of a newly selected input clock.




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