Features: • Wide range VCXO PLL feedback divider allows high frequency multiplication ratios and the input of very low input reference frequencies• Input clock frequency of <1kHz to 13.5MHz• Output clock frequency of 500kHz to 160MHz• PLL lock status output• VCXO-b...
MK2069-03: Features: • Wide range VCXO PLL feedback divider allows high frequency multiplication ratios and the input of very low input reference frequencies• Input clock frequency of <1kHz to 1...
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The MK2069-03 is a mixed analog / digital integrated circuit that is sensitive to PCB (printed circuit board) layout and external component selection. Used properly, the device will provide the same high performance expected from a canned VCXO-based hybrid timing device, but at a lower cost. To help avoid unexpected problems, the guidance provided in the sections below should be followed.
Stresses above the ratings listed below can cause permanent damage to the MK2069-03. These ratings, which are standard values for ICS industrial rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item |
Rating |
Supply Voltage, VDD | 7 V |
All Inputs and Outputs | -0.5 V to VDD+0.5 V |
Ambient Operating Temperature | -40 to +85 |
Storage Temperature | -65 to +150 |
Junction Temperature | 175 |
Soldering Temperature | 260 |
The MK2069-03 is a VCXO (Voltage Controlled Crystal Oscillator) based clock generator that offers system synchronization, jitter attenuation and frequency translation. MK2069-03 can accept an input clock over a wide range of frequencies and produces a de-jittered, low phase noise clock output. MK2069-03 is optimized for user configuration by providing access to all major PLL divider functions. No power-up programming is needed as configuration is pin selected. External VCXO loop filter components provide an additional level of performance tailoring.
The MK2069-03 features a very wide range VCXO PLL feedback divider, allowing high frequency multiplication ratios and therefore the input of very low input reference frequencies. The lock detector (LD) output of MK2069-03 serves as a clock status monitor. The clear (CLR) input enables rapid synchronization to the phase of a newly selected input clock, while eliminating the generation of extra clock cycles and wander caused by memory in the PLL feedback divider. CLR also serves as a temporary holdover function when kept low.