Features: • Packaged in 20 pin SOIC• 3.3 V ±5% operation• Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E• Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 ...
MK2049-35: Features: • Packaged in 20 pin SOIC• 3.3 V ±5% operation• Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Gen...
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Proximity Sensors Reed Switch 1 Form A Cylindrical Term.
Parameter |
Conditions |
Minimum |
Typical |
Maximum |
Units |
Supply Voltage, VDD | Referenced to GND |
7 |
V | ||
Inputs and Clock Outputs |
-0.5 |
VDD+0.5V |
V | ||
Ambient Operating Temperature | MK2049-34SI |
-40 |
85 |
||
Soldering Temperature | Max of 10 seconds |
250 |
|||
Storage temperature |
-65 |
150 |
The MK2049-35 is a Phase-Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-35 generates T1, E1, T3, E3, OC3/3, Gigabit Ethernet, and other communications frequencies. This allows for the generation of clocks frequency-locked to an 8 kHz backplane clock, simplifying clock synchronization in communications systems.
This part also has a jitter-attenuated Buffer capability. In this mode, the MK2049-35 is ideal for filtering jitter from with high jitter clocks.
ICS/MicroClock MK2049-35 can customize these devices for many other different frequencies. Contact your ICS/MicroClock representative for more details.