Features: • Packaged in 20 pin SOIC• Fixed input-output phase relationship on most clock selections• Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E• Accept multiple i...
MK2049-03: Features: • Packaged in 20 pin SOIC• Fixed input-output phase relationship on most clock selections• Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold...
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Proximity Sensors Reed Switch 1 Form A Cylindrical Term.
Parameter |
Conditions |
Minimum |
Typical |
Maximum |
Units |
Supply Voltage, VDD | Referenced to GND |
7 |
V | ||
Inputs Clock Outputs |
-0.5 |
VDD+.5V |
V | ||
Ambient Operating Temperature | MK2049-0xS |
0 |
70 |
||
MK2049-0xSI |
-40 |
85 |
|||
Soldering Temperature | Max of 10 seconds |
250 |
|||
Storage temperature |
-65 |
150 |
The MK2049-02 and MK2049-03 are Phase- Locked Loop (PLL) based clock synthesizers that accept multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-02/03 generate T1, E1, T3, E3, ISDN, xDSL, and other communications frequencies. This allows for the generation of clocks frequency-locked and phaselocked to an 8 kHz backplane clock, simplifying clock synchronization in communications systems. The MK2049-02/03 can also accept a T1, E1, T3, or E3 input clock and provide the same output for loop timing. All outputs are frequency-locked together and to the input.
These parts of MK2049-03 also have a jitter-attenuated buffer capability. In this mode, the MK2049-02/03 are ideal for filtering jitter from 27 MHz video clocks or other clocks with high jitter.
ICS/MicroClock MK2049-03 can customize these devices for many other different frequencies. Contact your ICS/MicroClock representative for more details.