MH32D72AKLA-75

Features:

- Utilizes industry standard 32M X 4 DDR Synchronous DRAMs in TSOP package , industry standard Registered Buffer   in TSSOP package , and industry standard PLL in TSSOP package.
- Vdd=Vddq=2.5v ±0.2V
- Double data rate architecture; two data transf ers per clock cycle
- Bidirectional, data strobe (DQS) is transmitted/receiv ed with data
- Dif f erential clock inputs (CLK and /CLK)
- data ref erenced to both edges of DQS
- /CAS latency - 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Auto precharge / All bank precharge controlled by A10
- 4096 ref resh cycles /64ms
- Auto ref resh and Self ref resh
- Row address A0-11 / Column address A0-9,11
- SSTL_2 Interf ace
- Module 1bank Conf igration
- Burst Ty pe - sequential/interleav e(programmable)
- Commands entered on each positiv e CLK edge


Application

Main memory unit for PC, PC server


Specifications

Symbol	Parameter	Condition	Ratings	Unit
Vdd	Supply Voltage	with respect to Vss	-0.5 ~ 3.7	V
VddQ	Supply Voltage for Output	with respect to VssQ	-0.5 ~ 3.7	V
VI	Input Voltage	with respect to Vss	-0.5 ~ Vdd+0.5	V
VO	Output Voltage	with respect to VssQ	-0.5 ~ VddQ+0.5	V
IO	Output Current		50	mA
Pd	Power Dissipation	Ta=25C	20	W
Topr	Operating Temperature		0 ~ 70	C
Tstg	Storage Temperature		-45 ~ 100	C

Description

The MH32D72AKLA is 33554432 - word x 72-bit Double Data Rate(DDR) Sy nchronous DRAM mounted module.

MH32D72AKLA consists of 18 industry standard 32M x 4 DDR Sy nchronous DRAMs in TSOP with SSTL_2 interf ace which achiev es v ery high speed data rate up to 133MHz.

This socket-ty pe memory MH32D72AKLA module is suitable for main memory in computer systems and easy to interchange or add modules.