Features: RASaccesstime(max.ns) CASaccesstime(max.ns) Addressaccesstime(max.ns) Cycletime(min.ns) -6 65 20 35 110 ·single 5V±5% supply·All input, output TTL compatible and low capacitance·1024 refresh cycle every 16.4ms(A0~A9)·Includes decoupling capacitor(0.22µFx19) ...
MH1M144CXTJ-6: Features: RASaccesstime(max.ns) CASaccesstime(max.ns) Addressaccesstime(max.ns) Cycletime(min.ns) -6 65 20 35 110 ·single 5V±5% supply·All input, output TTL compatible and low c...
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Features: Type name -----RASaccesstime(max.ns) -----CASaccesstime(max.ns) Addressaccess...
RAS access time (max.ns) |
CAS access time (max.ns) |
Addre ssaccess time (max.ns) |
Cycle time (min.ns) | |
-6 | 65 | 20 | 35 | 110 |
·single 5V±5% supply
· All input, output TTL compatible and low capacitance
·1024 refresh cycle every 16.4ms(A0~A9)
·Includes decoupling capacitor(0.22µFx19)
Symbol | Parameter | Conditions | Ratings | Unit |
Vcc | Supply voltage | With respect to Vss | -1 ~ 7 | V |
VI | Input voltage | -1 ~ 7 | V | |
V0 | Output voltage | -1 ~ 7 | V | |
I0 | Output current | 50 | mA | |
Pd | Power dissipation | Ta=25°C | 21.6 | W |
Topr | Operating temperature | 0 ~ 70 | °C | |
Tstg | Storage temperature | -40 ~ 100 | °C |
The MH1M144CXTJ is 1048576-word by 144-bit dynamic RAM module. This consists of nine industry standard 1Mx16 dynamic RAMs in TSOP and one industry standard input buffer in T-SSOP.
The mounting of TSOP on a card edge Dual Read Out package of MH1M144CXTJ provides any application where high densities and large quantities of memory are required.
MH1M144CXTJ is a socket type - memory modules, suitable for easy interchange or addition of modules.