MG65P

• 0.25m drawn 3-, 4-, and 5-layer metal CMOS
• Optimized 2.5-V core
• Optimized 3-V I/O
• CSA architecture availability
• 100 MHz embedded SDRAM cores up to 16 Mb per occurrence
• 77-ps typical logic gate propagation delay (for a 4x-drive inverter gate with a fanout of 2 and 0 mm of wire, operating at 2.5 V)
• Over 5.4M raw gates and 868 I/O pads using 60 staggered I/O
• User-configurable I/O with VSS, V_DD, TTL,3-state, and 1- to 24-mA options
• Slew-rate-controlled outputs for low-radiated noise
• H-clock tree cells which reduces the maximum skew for clock signals
• Low 0.2W/MHz/gate power dissipation
• User-configurable single- and dual-port memories (SRAM)
• Specialized IP cores and macrocells including 32-bit ARM7TDMI CPU, phase-locked loop (PLL), and peripheral component interconnect (PCI) cells
• Floorplanning for front-end simulation, backend layout controls, and link to synthesis
• Joint Test Action Group (JTAG) boundary scan and scan path Automatic Test Pattern Generation (ATPG)
• Support for popular CAE systems including Cadence, IKOS, Mentor Graphics, Model Technology, Inc. (MTI), Synopsys, and Viewlogic

1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions in the other specifications of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Oki's 0.25 m MG63P/64P/65P Application-Specific Integrated Circuit (ASIC) provides the ability to embed large blocks of Synchronous DRAM (SDRAM) into an embedded array architecture called the Customer Structured Array (CSA). Utilizing Oki's leadership in DRAM technologies and wide experience of embedding SDRAM in logic products, Oki is able to integrate SDRAM and ASIC technology. The merged DRAM/ASIC process efficiently implements the Oki stacked capacitor memory cell. The MG63P/64P/65P CSA series uses three, four, and five metal process layers, respectively, on 0.25 m drawn (0.18 m L-effective) CMOS technology. The semiconductor process is adapted from Oki's production- proven 64- Mbit DRAM manufacturing process.

The 0.25  m MG63P/64P/65P  family provides significant performance, density, and power improvement over previous 0.30 m and 0.35 m technologies. An innovative 4-transistor cell structure provides 30 to 50% less power and 30 to 50% more usable gates than traditional cell designs. The Oki 0.25 m family operates using 2.5-V VDD core with optimized 3-V I/O buffers. The 3-, 4-, and 5-layer metal MG63P/64P/65P CSA series contains 21 devices each, offering up to 868 I/O pads and over 5.4M raw gates. These CSA array sizes are designed to fit the most popular quad flat pack (QFP), low profile QFPs (LQFPs), thin QFPs (TQFPs), and plastic ball grid array (PBGA) packages. Oki uses the Artisan Components memory compiler which provides high performance, embedded synchronous single- and dual-port SRAM macrocells for CSA designs. As such, the MG63P/64P/65P series is suited to memory-intensive ASICs and high volume designs where fine tuning of package size produces significant cost or real-estate savings.The embedded SDRAM represents part of Oki's menu of major IP core functions for the 0.25 m ASIC products. Other functions include ARM7TDMI, Gb Ethernet MAC, PLL, PCI and others in planning.