MG2RTP

Ambient temperature under bias (TA)
Military -55 to +125°C
Junction temperature TJ < TA + 20°C
Storage temperature -65 to +150°C
TTL/CMOS:
Supply voltage VDD-0.5 V to +6 V
I/O voltage -0.5 V to VDD + 0.5 V

Note: Stresses above those listed may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended period may affect device reliability.

The MG2RTP series is a 0.5 micron, array based, CMOS product family. Several arrays up to 490k cells cover all system integration needs. The MG2RTP is manufactured using a 0.5 micron drawn, 3 metal layers CMOS process.

The MG2RTP series base cell architecture provides high routability of logic with extremely dense compiled memories: RAM and DPRAM. ROM can be generated using synthesis tools.

Accurate control of clock distribution MG2RTP can be achieved by PLL hardware and CTS (Clock Tree Synthesis) software. New noise prevention techniques of MG2RTP are applied in the array and in the periphery: three or more independent supplies, internal decoupling, customisation dependent supply routing, noise filtering, skew controlled I/Os, low swing differential I/Os, all contribute to improve the noise immunity and reduce the emission level.