MG2590

Features:

Full Range of Matrices up to 700k Cells
0.5 m Drawn CMOS, 3 Metal Layers, Sea of Gates
RAM, DPRAM, FIFO Compilers
Library Optimised for Synthesis, Floor Plan & Automatic Test Generation (ATG)
High Speed Performances :
  200 ps Typical Gate Delay @5 V
  typical 625 MHz Toggle Frequency @5 V and 360 MHz @3.3 V
High System Frequency Skew Control :
  250 MHz PLL for Clock Generation
  Clock Tree Synthesis Software
3 & 5 Volts Operation; Single or Dual Supply Modes
Low Power Consumption :
  0.6 W/Gate/MHz @3 V
  2.2 W/Gate/MHz @5 V
Integrated Power on Reset
Matrices With a max of 582 full programmable Pads
Standard 3, 6, 12 and 24mA I/Os
Versatile I/O Cell : Input, Output, I/O, Supply, Oscillator
CMOS/TTL/PCI Interface
ESD (2 kV) And Latch-up Protected I/O
High Noise & EMC Immunity :
  I/O with Slew Rate Control
  Internal Decoupling
  Signal Filtering between Periphery & Core
  Application Dependent Supply Routing & Several
Wide Range of Packages Including PGA, CQFP, PLCC PQFP, BGA, SSOP ...
Delivery in Die Form
Advanced CAD Support : Floor Plan, Proprietary Delay Models, Timing Driven Layout, Power Management
Cadence, Mentor, Vital & Synopsys Reference Platforms
EDIF & VHDL Reference Formats
Available In Commercial, Industrial and Military Quality  Grades
Special Versions on Radiation Tolerant Process: see MG2RT and MG2RTP specification.
QML Q


Specifications

Ambient temperature under bias (TA)
  Commercial . . . . . . . . . . .  . . . . . . . . . . . . . . . . . 0°C to +70
  Junction temperature . .  . . . . . . . . . . . . . . . . . . TJ < TA + 20
  Storage temperature . . . . . . . . . . . . . . . . . . . . 65 to +150
TTL/CMOS :
  Supply voltage VDD . . . . . . . . . . . . . . . . . . . . . 0.5 V to +6 V
  I/O voltage . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VDD + 0.5 V

Stresses above those listed may cause permanent damage to the device. Explosure to absolute maximum rating conditions for extended period may affect device reliability.


Description

The MG2 series is a 0.5 micron, array based, CMOS product family. Several arrays up to 700k cells cover all system integration needs. The MG2 is manufactured using SCMOS3/2, a 0.5 micron drawn, 3 metal layers CMOS process.
 
The MG2 series base cell architecture provides high routability of logic with extremely dense compiled memories : RAM, DPRAM and FIFO. ROM MG2 series can be generated using synthesis tools. For instance, the largest array is capable of integrating 128K bits of DPRAM with 128K bits of ROM and over 300,000 random gates.

Accurate control of clock distribution MG2 series can be achieved by PLL hardware and CTS (Clock Tree Synthesis) software. New noise prevention techniques of MG2 series are applied in the array and in the periphery : Three or more independent supplies, internal decoupling, customisation dependent supply routing, noise filtering, skew controlled I/Os, low swing differential I/Os, all contribute to improve the noise immunity and reduce the emission level.

The MG2 is supported by an advanced software environment based on industry standards linking proprietary and commercial tools. Cadence, Mentor, Synopsys and VHDL are the reference front end tools. Floor planning associated with timing driven layout provides a short back end cycle.

The MG2 family continues the TEMIC offering in array based commercial, industrial and military circuits.