MG2142P

Features:

Full Range of Matrices up to 490k Cells
0.5 m Drawn CMOS, 3 Metal Layers, Sea of Gates
RAM, DPRAM, FIFO Compilers
Library Optimised for Synthesis, Floor Plan & Automatic Test Generation (ATG)
3 & 5 Volts Operation; Single or Dual Supply Modes
High Speed Performances:
  640 ps max. NAND2 propagation Delay @5 V and FO = 1/4 FO max.
  min. 440 MHz Toggle Frequency @4.5 V, and 230 MHz @2.7 V.
Programmable PLL available on request
High System Frequency Skew Control:
  200 MHz max. PLL for Clock Generation @4.5 V.
  Clock Tree Synthesis Software
Low Power Consumption:
  2 W/Gate/MHz @5 V
  0.6 W/Gate/MHz @3 V
Matrices With a max of 484 full programmable Pads
Standard 3, 6, 12 and 24mA I/Os
Versatile I/O Cell: Input, Output, I/O, Supply, Oscillator
CMOS/TTL/PCI Interface
ESD (2 kV) And Latch-up Protected I/O
Selection of MQFPs package up to 352 pins
High Noise & EMC Immunity:
  I/O with Slew Rate Control
  Internal Decoupling
  Signal Filtering between Periphery & Core
  Application Dependent Supply Routing & Several
Wide range of hermetic ceramic multilayer packages: for plastic packages, call factory.
Delivery in Die Form
Advanced CAD Support : Floor Plan, Proprietary Delay Models, Timing Driven Layout, Power Management
Cadence, Mentor, Vital & Synopsys Reference Platforms
EDIF & VHDL Reference Formats
Available In Commercial, Industrial, Military and Space Quality Grades (SCC, MILI38534, MILPRF38535)
Latch up immune
Total dose better than 300 Krads (TM1019.5)
QML Q & V .


Specifications

Ambient temperature under bias (TA)
  Military . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 to +125°C
  Junction temperature . . . . . . . . . . . . . . . . . . . . TJ < TA + 20°C
  Storage temperature . . . . . . . . . . . . . . . . . . . . 65 to +150°C
TTL/CMOS :
  Supply voltage VDD . . . . . . . . . . . . . . . . . . . . . 0.5 V to +6 V
  I/O voltage . . . . . . .  . . . . . . . . . . . . . . . . . . . . 0.5 V to VDD + 0.5 V

Stresses above those listed may cause permanent damage to the device. Explosure to absolute maximum rating conditions for extended period may affect device reliability.


Description

The MG2RTP series is a 0.5 micron, array based, CMOS product family. Several arrays up to 490k cells cover all system integration needs. The MG2RTP is manufactured using SCMOS3/2RTP, a 0.5 micron drawn, 3 metal layers CMOS process, the "radiation tolerant" version of SCMOS3/2.

The MG2RTP series base cell architecture provides high routability of logic with extremely dense compiled memories : RAM, DPRAM and FIFO. ROM can be generated using synthesis tools.

Accurate control of clock distribution MG2RTP series can be achieved by PLL hardware and CTS (Clock Tree Synthesis) software. New noise prevention techniques MG2RTP series are applied in the array and in the periphery : Three or more independent supplies, internal decoupling, customisation dependent supply routing, noise filtering, skew controlled I/Os, low swing differential I/Os, all contribute to improve the noise immunity and reduce the emission level.

The MG2RTP is supported by an advanced software environment based on industry standards linking proprietary and commercial tools. Cadence, Mentor, Synopsys and VHDL are the reference front end tools. Floor planning associated with timing driven layout provides a short back end cycle.

The MG2RTP family extends the TEMIC offering in array based rad hard space circuits.

MG2RTP series's Library allows straight forward migration from the MG1, MG1RT, MG2 and MG2RT Sea of Gates.