Features: Full Range of Matrices up to 480k Cells0.6 µm Drawn CMOS, 3 Metal Layers, Sea of GatesHigh Integration Level : 1000k Equivalent Gates in Memory Intensive ApplicationsRAM, DPRAM, FIFO CompilersLibrary Optimised for Synthesis, Floor Plan & Automatic Test Generation (ATG)High Spee...
MG1RT: Features: Full Range of Matrices up to 480k Cells0.6 µm Drawn CMOS, 3 Metal Layers, Sea of GatesHigh Integration Level : 1000k Equivalent Gates in Memory Intensive ApplicationsRAM, DPRAM, FIFO...
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
The MG1RT series is a 0.6 micron 3 metal layers, arraybased, CMOS product family offering a new frontier in integration and speed. Several arrays up to 500k cells cover all system integration needs. The MG1RT is manufactured using SCMOS 2/2 RT, a 0.6 micron drawn, radiation tolerant, 3 metal layers CMOS process.
The advanced feature size of the MG1RT translates into high performance with gate delays of 250 ps and toggle frequency of 350 MHz. Both 3V and 5V operation are possible for optimum speed/power trade off.
The MG1RT series base cell architecture provides high routability of logic with extremely dense compiled memories : ROM, RAM and DPRAM. For instance, the largest array is capable of integrating 128K bits of DPRAM with 128K bits of ROM and over 200,000 random gates.
Accurate control of clock distribution MG1RT can be achieved by PLL hardware and CTS (Clock Tree Synthesis) software. New noise prevention techniques of MG1RT are applied in the array and in the periphery : three or more independent supplies, internal decoupling, customisation dependent supply routing, noise filtering, skew controlled I/Os, low swing differential I/Os, all contribute to improve the noise immunity and reduce the emission level.
The basic library is designed for optimum speed and area efficiency with logic synthesis software; for example, the register element is 25% smaller than in most competitors libraries. The new delay model of MG1RT included in the simulation libraries gives unprecedented accuracy of the pre-layout and post- layout simulations.
The high level function libraries of MG1RT include many common peripheral controllers and several complex circuits derived from the Atmel Wireless & Microcontrollers image and network ASSPs offering.
The MG1RT is supported by an advanced software environment based on industry standards linking proprietary and commercial tools. Cadence, Mentor, Synopsys and VHDL are the reference front end tools. Floor planning associated with timing driven layout provides a short back end cycle.
The MG1RT family continues the Atmel Wireless & Microcontrollers offering in array based for commercial, automotive, industrial, military and space circuits. Design compatibility with previous CMOS and BiCMOS series is assured.