MG1350E

Features:

Full Range of Matrices up to 480k Cells
0.6 m Drawn CMOS, 3 Metal Layers, Sea of Gates
High Integration Level : 1000k Equivalent Gates in Memory Intensive Applications
RAM, DPRAM, FIFO Compilers
Library Optimised for Synthesis, Floor Plan & Automatic Test Generation (ATG)
High Speed Performances :
250 ps Typical Gate Delay
350 MHz Toggle Frequency
High System Frequency Skew Control :
250 MHz PLL for Clock Generation
Clock Tree Synthesis Software
3 & 5 Volts Operation; Single or Dual Supply Modes
Low Power Consumption :
0.9 W/Gate/Mhz @3 V
2.4 W/Gate/Mhz @5 V
Integrated Power on Reset
Matrices With More than 500 Pads
Versatile I/O Cell : Input, Output, I/O, Supply, Oscillator
MQFPs packages, up to 352 pins
GTL & BTL Backplane Driver & Differential Receiver
Configurable Drive Up To 48 mA
ESD (4 kV) And Latch-up Protected I/O
High Noise & EMC Immunity :
I/O with Slew Rate Control
Internal Decoupling
Signal Filtering between Periphery & Core
Application Dependent Supply Routing & Several Independent Supply Sources
Wide Range of Packages
Delivery in Die Form
Advanced CAD Support : Floor Plan, Proprietary Delay Models, Timing Driven Layout, Power Management
Cadence, Mentor & Synopsys Reference Platforms
EDIF & VHDL Reference Formats
QML Q and V


Specifications

Ambient temperature under bias (TA)
  Military . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 to +125°C
  Junction temperature .  . . . . . . . . . . . . . . . . . . TJ < TA + 20°C
  Storage temperature . . . . . . . . . . . . . . . . . . . . 65 to +150
TTL/CMOS :
  Supply voltage VDD . . . . . . . . . . . . . . . . . . . . . 0.5 V to +7 V
  I/O voltage . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VDD + 0.5 V

Stresses above those listed may cause permanent damage to the device.


Description

The MG1RT series is a 0.6 micron 3 metal layers, array based, CMOS product family offering a new frontier in integration and speed. Several arrays up to 500k cells cover all system integration needs. The MG1RT is manufactured using SCMOS 2/2 RT, a 0.6 micron drawn, radiation tolerant, 3 metal layers CMOS process.

The advanced feature size of the MG1RT translates into high performance with gate delays of 250 ps and toggle frequency of 350 MHz. Both 3V and 5V operation are possible for optimum speed/power trade off.

The MG1RT series base cell architecture provides high routability of logic with extremely dense compiled memories : ROM, RAM and DPRAM. For instance, the largest array is capable of integrating 128K bits of DPRAM with 128K bits of ROM and over 200,000 random gates.

Accurate control of clock distribution can be achieved by PLL hardware and CTS (Clock Tree Synthesis) software. New noise prevention techniques are applied in the array and in the periphery : three or more independent supplies, internal decoupling, customisation dependent supply routing, noise filtering, skew controlled I/Os, low swing differential I/Os, all contribute to improve the noise immunity and reduce the emission level.

The basic library is designed for optimum speed and area efficiency with logic synthesis software; for example, the register element is 25% smaller than in most competitors libraries. The new delay model included in the simulation libraries gives unprecedented accuracy of the pre-layout and post- layout simulations.

The high level function libraries of MG1RT include many common peripheral controllers and several complex circuits derived from the MHS image and network ASSPs offering.

The MG1RT is supported by an advanced software environment based on industry standards linking proprietary and commercial tools. Cadence, Mentor, Synopsys and VHDL are the reference front end tools. Floor planning associated with timing driven layout provides a short back end cycle.

The MG1RT family continues the MHS offering in array based for commercial, automotive, industrial, military and space circuits. Design compatibility with previous CMOS and BiCMOS series is assured.