MG1004

Features:

Full Range of Matrices up to 500k Cells
0.6 m Drawn CMOS, 3 Metal Layers, Sea of Gates
RAM, DPRAM, FIFO Compilers
Library Optimised for Synthesis, Floor Plan & Automatic Test Generation (ATG)
High Speed Performances :
  250 ps Typical Gate Delay @5 V
  350 MHz Toggle Frequency @5 V
High System Frequency Skew Control :
  250 MHz PLL for Clock Generation
  Clock Tree Synthesis Software
3 & 5 Volts Operation; Single or Dual Supply Modes
Low Power Consumption :
  0.9 W/Gate/MHz @3 V
  2.4 W/Gate/MHz @5 V
Integrated Power on Reset
Matrices With More than 500 Pads
Standard 3, 6, 12m, 24mA I/Os, parallelism up to 48mA
Versatile I/O Cell : Input, Output, I/O, Supply, Oscillator
CMOS/TTL/PCI Interface
ESD (2 kV) And Latch-up Protected I/O
High Noise & EMC Immunity :
  I/O with Slew Rate Control
  Internal Decoupling
  Signal Filtering between Periphery & Core
  Application Dependent Supply Routing & Several Independent Supply Sources
Wide Range of Packages Including PGA & CQFP
Delivery in Die Form
Advanced CAD Support : Floor Plan, Proprietary Delay Models, Timing Driven Layout, Power Management
Cadence, Compass, Mentor & Synopsys Reference Platforms
EDIF & VHDL Reference Formats
Upward Compatibility With MC & MF Gate Arrays, MCM Composite Arrays.
Full Compatibility with MG1M Composite Sea of Gates Series
Available In Commercial, Industrial, Automotive, Military & Space Quality Grades
Special Versions on Radiation Tolerant Process
QML Q


Specifications

Ambient temperature under bias (TA)
  Military . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 to +125
  Junction temperature . . . . . . . . . . . . . . . . . . . . TJ < TA + 20
  Storage temperature . . . . . . . . . . . . . . . . . . . . 65 to +150
TTL/CMOS :
  Supply voltage VDD . . . . . . . . . . . . . . . . . . . . . 0.5 V to +7 V
  I/O voltage . . . . . . .  . . . . . . . . . . . . . . . . . . . . 0.5 V to VDD + 0.5 V

Stresses above those listed may cause permanent damage to the device. Explosure to absolute maximum rating conditions for extended period may affect device reliability.


Description

The MG1 series is a 0.6 micron, array based, CMOS product family offering a new frontier in integration and speed. Several arrays up to 500k cells cover all system integration needs. The MG1 is manufactured using SCMOS 2/2, a 0.6 micron drawn, 3 metal layers CMOS process.

The MG1 series base cell architecture provides high routability of logic with extremely dense compiled memories : RAM, DPRAM and FIFO, ROM can be generated using synthesis tools. For instance, the largest array is capable of integrating 128K bits of DPRAM with 128K bits of ROM and over 200,000 random gates.

Accurate control of clock distribution of MG1 series  can be achieved by PLL hardware and CTS (Clock Tree Synthesis) software. New noise prevention techniques are applied in the array and in the periphery : Three or more independent supplies, internal decoupling, customisation dependent supply routing, noise filtering, skew controlled I/Os, low swing differential I/Os, all contribute to improve the noise immunity and reduce the emission level.

The MG1 is supported by an advanced software environment based on industry standards linking proprietary and commercial tools. Cadence, Compass, Mentor, Synopsys and VHDL are the reference front end tools. Floor planning associated with timing driven layout provides a short back end cycle.

The MG1 family continues the TEMIC offering in array based commercial, automotive, industrial, military and space circuits.