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MCM72F9

Features: • Single 3.3 V + 10%, 5% Power Supply• Plug and Pin Compatibility with 2MB and 4MB• Multiple Clock Pins for Reduced Loading• All Inputs and Outputs are LVTTL Compatible• Byte Write Capability• Fast SRAM Access Times: 8/9/12 ns• Decoupling Capaci...

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SeekIC No. : 004417957 Detail

MCM72F9: Features: • Single 3.3 V + 10%, 5% Power Supply• Plug and Pin Compatibility with 2MB and 4MB• Multiple Clock Pins for Reduced Loading• All Inputs and Outputs are LVTTL Compa...

MCM72F9 Data Sheet

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Part Number:
MCM72F9
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/27

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Product Details

Description



Features:

• Single 3.3 V + 10%, 5% Power Supply
• Plug and Pin Compatibility with 2MB and 4MB
• Multiple Clock Pins for Reduced Loading
• All Inputs and Outputs are LVTTL Compatible
• Byte Write Capability
• Fast SRAM Access Times: 8/9/12 ns
• Decoupling Capacitors for Each Fast Static RAM
• High Quality MultiLayer FR4 PWB With Separate Power and Ground Planes
• Amp Connector, Part Number: 3900644
• 168Pin DIMM Module


Specifications

Rating Symbol Value Unit
Power Supply Voltage VDD 0.5 to + 4.6 V
Voltage Relative to VSS (See Note 2) Vin, Vout 0.5 to VDD + 0.5 V
Input Voltage Three State I/O (See Note 2) VIT 0.5 to VDD + 0.5 V
Output Current (per I/O) Iout ± 20 mA
Power Dissipation MCM72F8
MCM72F9		 PD 4.6
9.2		 W
Ambient Temperature TA 0 to 70
Die Temperature TJ 110
Temperature Under Bias Tbias 10 to + 85
Storage Temperature Tstg 55 to + 125



Description

The MCM72F8 (2MB) is configured as 256K x 72 bits and the MCM72F9 (4MB) is configured as 512K x 72 bits. Both are packaged in a 168pin dualinline memory module DIMM. Each module uses Motorola's 3.3 V 256K x 18 bit flowthrough BurstRAMs.

Address (A), data inputs (DQ, DP) of the MCM72F9, and all control signals except output enable (G) are clock (K) controlled through positiveedgetriggered noninverting registers.

Write cycles of the MCM72F9 are internally selftimed and initiated by the rising edge of the clock (K) input. This feature provides increased timing flexibility for incoming signals. Synchronous byte write (W) allows writes to either individual bytes or to both bytes.




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