MCM56824A

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.

The MCM56824A is a 196,608 bit static random access memory organized as 8,192 words of 24 bits. The device integrates an 8K x 24 SRAM core with multiple chip enable inputs, output enable, and an externally controlled single address pin multiplexer. These functions allow for direct connection to the Motorola DSP56001 Digital Signal Processor and provide a very efficient means for implementation of a reduced parts count system requiring no additional interface logic.

The availability of multiple chip enable (E1 and E2) and output enable (G) inputs provides for greater system flexibility when multiple devices are used. With either chip enable input unasserted, the device will enter standby mode, useful
in lowpower applications. A single onchip multiplexer selects A12 or X/Y as the highest order address input depending upon the state of the V/S control input. This feature allows one physical static RAM component to efficiently store program and vector or scalar operands by dynamically repartitioning the RAM array. Typical applications will logically map vector operands into upper memory with scalar operands being stored in lower memory. By connecting
DSP56001address A15 to the VECTOR/SCALAR (V/S) MUX control pin, such partitioning can occur with no additional components. This allows efficient utilization of the RAM resource irrespective of operand type. See application diagrams at the end of this document for additional information.

Multiple power and ground pins have been utilized to minimize effects induced by output noise.

The MCM56824A is available in a 52 pin plastic leaded chipcarrier (PLCC) and a 9 x 10 grid, 86 bump surface mount PBGA.
• Single 5 V ± 10% Power Supply
• Fast Access and Cycle Times: 20/25/35 ns Max
• Fully Static Read and Write Operations
• Equal Address and Chip Enable Access Times
• Single Bit OnChip Address Multiplexer
• Active High and Active Low Chip Enable Inputs
• Output Enable Controlled Three State Outputs
• High Board Density PLCC Package
• Low Power Standby Mode
• Fully TTL Compatible