Description The MCM36100 is a 36M dynamic random access memory (DRAM) module organized as 1,048,576 x 36 bits.The module is a 72-lead single-in-line memory module (SIMM) consisting of eight MCM54400A DRAMS housed in standard 300 mil SOJ packages and four CMOS 1 M x 1 DRAMS housed in 20/26 lead SO...
MCM36100: Description The MCM36100 is a 36M dynamic random access memory (DRAM) module organized as 1,048,576 x 36 bits.The module is a 72-lead single-in-line memory module (SIMM) consisting of eight MCM5440...
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The MCM36100 is a 36M dynamic random access memory (DRAM) module organized as 1,048,576 x 36 bits.The module is a 72-lead single-in-line memory module (SIMM) consisting of eight MCM54400A DRAMS housed in standard 300 mil SOJ packages and four CMOS 1 M x 1 DRAMS housed in 20/26 lead SOJ packages, mounted on a substrate along with a 0.22 F (min) decoupling capacitor mounted under each DRAM. The MCM54400A is a CMOS high-speed dynamic random access memory organized as 1,048,576 four-bit words and fabricated with CMOS silicon-gate process technology.
The MCM36100 has the following features include:(1)three-state data output;(2)early-write common iio capability; (3)fast page mode capability;(4)TTL-compatible inputs and outputs;(5)hidden refresh;(6)1024 cycle refresh: 16 ms (max);(7)consists of eight 1 M x 4 DRAMS, Four 1 M x 1 DRAMS, and Twelve 0.22 F (min) decoupling capacitors;(8)unlatched data out at cycle end allows two dimensional chip selection.The dynamic RAM design is based on capacitor charge storage for each bit in the array. This charge will tend to degrade with time and temperature. Each bit must be periodically refreshed (recharged) to maintain the correct bit state. Bits in the MCM36100 require refresh every 16 milliseconds.
The absolute maximum ratings of the MCM36100 are:(1)voltage relative to Vss:-1 to +7V;(2)data output current per DQ pin:50mA;(3)power disspation:8.4W;(4)storage temperature range:-55 to +125°C;(5)operating temperature:0 to +70°C;(6)power supply voltage:-1 to +7V.This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high-impedance circuits.This is accomplished by cycling through the 1024 row addresses in sequence within the specified refresh time. All the bits on a row are refreshed simultaneously when the row is addressed. Distributed refresh implies a row refresh every 15.6 microseconds for the MCM36100. Burst refresh, a refresh of all 1024 rows consecutively, must be performed every 16 milliseconds on the MCM36100.