MCF5235EC

• Version 2 ColdFire variable-length RISC processor core
- Static operation
- 32-bit address and data path on-chip
- Processor core runs at twice the bus frequency
- Sixteen general-purpose 32-bit data and address registers
- Implements the ColdFire Instruction Set Architecture, ISA_A+, with extensions to support the user stack pointer register, and 4 new instructions for improved bit processing
- Enhanced Multiply-Accumulate (EMAC) unit with four 48-bit accumulators to support 32-bit signal processing algorithms
- Illegal instruction decode that allows for 68K emulation support
• Enhanced Time Processor Unit (eTPU)
- Event triggered VLIW processor timer subsystem
- 32 channels
- 24-bit timer resolution
- 6 Kbyte of code memory and 1.5 Kbyte of data memory
- Variable number of parameters allocatable per channel
- Double match/capture channels
- Angle mode support
- DMA and interrupt request support
- Nexus Class 1 Debug support
• System debug support
- Integrated debug supports both ColdFire Debug and Nexus class 1 features on a single port with cross triggering operations for ease of use
- Unified programming model including both ColdFire and Nexus debug registers
- Real time trace for determining dynamic execution path
- Background debug mode (BDM) for in-circuit debugging
- Real time debug support, with two user-visible hardware breakpoint registers (PC and address with optional data) that can be configured into a 1- or 2-level trigger
• On-chip memories
- 8-Kbyte cache, configurable as instruction-only, data-only, or split I-/D-cache
- 64-Kbyte dual-ported SRAM on CPU internal bus, accessible by core and non-core bus masters (e.g., DMA, FEC)
• Fast Ethernet Controller (FEC)
- 10 BaseT capability, half duplex or full duplex
- 100 BaseT capability, half duplex or full duplex
- On-chip transmit and receive FIFOs
- Built-in dedicated DMA controller
- Memory-based flexible descriptor rings
- Media independent interface (MII) to external transceiver (PHY)
• FlexCAN Modules (up to 2)
- Full implementation of the CAN protocol specification version 2.0B
Standard Data and Remote Frames (up to 109 bits long)
Extended Data and Remote Frames (up to 127 bits long)
08 bytes data length
Programmable bit rate up to 1 Mbit/sec
- Flexible Message Buffers (MBs), totalling up to 16 message buffers of 08 bytes data length each, configurable as Rx or Tx, all supporting standard and extended messages
- Unused MB space can be used as general purpose RAM space
- Listen only mode capability
- Content-related addressing
- Three programmable mask registers: global (for MBs 0-13), special for MB14 and special for MB15
- Programmable transmit-first scheme: lowest ID or lowest buffer number
- "Time stamp" based on 16-bit free-running timer
- Global network time, synchronized by a specific message
• Three Universal Asynchronous Receiver Transmitters (UARTs)
- 16-bit divider for clock generation
- Interrupt control logic
- Maskable interrupts
- DMA support
- Data formats can be 5, 6, 7 or 8 bits with even, odd or no parity
- Up to 2 stop bits in 1/16 increments
- Error-detection capabilities
- Modem support includes request-to-send (UnRTS) and clear-to-send (UnCTS) lines
- Transmit and receive FIFO buffers
• I2C Module
- Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads
- Fully compatible with industry-standard I2C bus
- Master or slave modes support multiple masters
- Automatic interrupt generation with programmable level
• Queued Serial Peripheral Interface (QSPI)
- Full-duplex, three-wire synchronous transfers
- Up to four chip selects available
- Master mode operation only
- Programmable master bit rates
- Up to 16 pre-programmed transfers
• Four 32-bit DMA Timers
- 13-ns resolution at 75 MHz
- Programmable sources for clock input, including an external clock option
- Programmable prescaler
- Input-capture capability with programmable trigger edge on input pin
- Output-compare with programmable mode for the output pin
- Free run and restart modes
- Maskable interrupts on input capture or reference-compare
- DMA trigger capability on input capture or reference-compare
• Four Periodic Interrupt Timers (PITs)
- 16-bit counter
- Selectable as free running or count down
• Software Watchdog Timer
- 16-bit counter
- Low power mode support
• Phase Locked Loop (PLL)
- Crystal or external oscillator reference
- 8 to 25 MHz reference frequency for normal PLL mode
- 24 to 75 MHz oscillator reference frequency for 2:1 mode
- Separate clock output pin
• Interrupt Controllers (x2)
- Support for up to 110 interrupt sources organized as follows:
103 fully-programmable interrupt sources
7 fixed-level external interrupt sources
- Unique vector number for each interrupt source
- Ability to mask any individual interrupt source or all interrupt sources (global mask-all)
- Support for hardware and software interrupt acknowledge (IACK) cycles
- Combinatorial path to provide wake-up from low power modes
• DMA Controller
- Four fully programmable channels
- Dual-address and single-address transfer support with 8-, 16- and 32-bit data capability along with support for 16-byte (4 * 32-bit) burst transfers
- Source/destination address pointers that can increment or remain constant
- 24-bit byte transfer counter per channel
- Auto-alignment transfers supported for efficient block movement
- Bursting and cycle steal support
- Software-programmable connections between the 12 DMA requesters in the UARTs (3),
32-bit timers (4) plus external logic (4) the four DMA channels and the eTPU (1)
• External Bus Interface
- Glueless connections to external memory devices (e.g., SRAM, Flash, ROM, etc.)
- SDRAM controller supports 8-, 16-, and 32-bit wide memory devices
- Support for n-1-1-1 burst fetches from page mode Flash
- Glueless interface to SRAM devices with or without byte strobe inputs
- Programmable wait state generator
- 32-bit bidirectional data bus
- 24-bit address bus
- Up to eight chip selects available
- Byte/write enables (byte strobes)
- Ability to boot from external memories that are 8, 16, or 32 bits wide
• Chip Integration Module (CIM)
- System configuration during reset
- Selects one of four clock modes
- Sets boot device and its data port width
- Configures output pad drive strength
- Unique part identification number and part revision number
- Reset
Separate reset in and reset out signals
Six sources of reset: Power-on reset (POR), External, Software, Watchdog, PLL loss of clock, PLL loss of lock
Status flag indication of source of last reset
• General Purpose I/O interface
- Up to 142 bits of general purpose I/O
- Bit manipulation supported via set/clear functions
- Unused peripheral pins may be used as extra GPIO
• JTAG support for system level board testing

The MCF5235EC is a family of highly-integrated 32-bit Table of Contents microcontrollers based on the V2 ColdFire microarchitecture. Featuring a 16 or 32 channel eTPU, 64 Kbytes of internal SRAM, a 2-bank SDRAM controller, four 32-bit timers with dedicated DMA, a 4 channel DMA controller, up to 2 CAN modules, 3 UARTs and a queued SPI, the MCF523x family has been designed for general purpose industrial control applications. It is also a high-performance upgrade for users of the MC68332. This document provides an overview of the MCF523x microcontroller family, as well as detailed descriptions of the mechanical and electrical characteristics of the MCF5235EC.

The MCF5235EC family is based on the Version 2 ColdFire reduced instruction set computing (RISC) microarchitecture operating at a core frequency of up to 150 MHz and bus frequency up to 75 MHz.