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MC9S12NE64

Features: • 16-bit HCS12 core - HCS12 CPU Upward compatible with M68HC11 instruction set Interrupt stacking and programmer's model identical to M68HC11 Instruction queue Enhanced indexed addressing - Memory map and interface (MMC) - Interrupt control (INT) - Background debug mode (BDM) -...

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SeekIC No. : 004417442 Detail

MC9S12NE64: Features: • 16-bit HCS12 core - HCS12 CPU Upward compatible with M68HC11 instruction set Interrupt stacking and programmer's model identical to M68HC11 Instruction queue Enhanced indexed a...

MC9S12NE64 Data Sheet

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Part Number:
MC9S12NE64
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/27

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Product Details

Description



Features:

• 16-bit HCS12 core
  - HCS12 CPU
  Upward compatible with M68HC11 instruction set
  Interrupt stacking and programmer's model identical to M68HC11
  Instruction queue
  Enhanced indexed addressing
  - Memory map and interface (MMC)
  - Interrupt control (INT)
  - Background debug mode (BDM)
  - Enhanced debug12 module, including breakpoints and change-of-flow trace buffer (DBG)
  - Multiplexed expansion bus interface (MEBI) - available only in 112-pin package version
• Wakeup interrupt inputs
  - Up to 21 port bits available for wakeup interrupt function with digital filtering
• Memory
  - 64K bytes of FLASH EEPROM
  - 8K bytes of RAM
• Analog-to-digital converter (ATD)
  - One 8-channel module with 10-bit resolution
  - External conversion trigger capability
• Timer module (TIM)
  - 4-channel timer
  - Each channel configurable as either input capture or output compare
  - Simple PWM mode
  - Modulo reset of timer counter
  - 16-bit pulse accumulator
  - External event counting
  - Gated time accumulation
• Serial interfaces
  - Two asynchronous serial communications interface (SCI)
  - One synchronous serial peripheral interface (SPI)
  - One inter-IC bus (IIC)
• Ethernet Media access controller (EMAC)
  - IEEE 802.3 compliant
  - Medium-independent interface (MII)
  - Full-duplex and half-duplex modes
  - Flow control using pause frames
  - MII management function
  - Address recognition
  Frames with broadcast address are always accepted or always rejected
  Exact match for single 48-bit individual (unicast) address
  Hash (64-bit hash) check of group (multicast) addresses
  Promiscuous mode
• Ethertype filter
• Loopback mode
• Two receive and one transmit Ethernet buffer interfaces
• Ethernet 10/100 Mbps transceiver (EPHY)
  - IEEE 802.3 compliant
  - Digital adaptive equalization
  - Half-duplex and full-duplex
  - Auto-negotiation next page ability
  - Baseline wander (BLW) correction
  - 125-MHz clock generator and timing recovery
  - Integrated wave-shaping circuitry
  - Loopback modes
• CRG (clock and reset generator module)
  - Windowed COP watchdog
  - Real-time interrupt
  - Clock monitor
  - Pierce oscillator
  - Phase-locked loop clock frequency multiplier
  - Limp home mode in absence of external clock
  - 25-MHz crystal oscillator reference clock
• Operating frequency
  - 50 MHz equivalent to 25 MHz bus speed for single chip
  - 32 MHz equivalent to 16 MHz bus speed in expanded bus modes
• Internal 2.5-V regulator
  - Supports an input voltage range from 3.3 V ± 5%
  - Low-power mode capability
  - Includes low-voltage reset (LVR) circuitry
• 80-pin TQFP-EP or 112-pin LQFP package
  - Up to 70 I/O pins with 3.3 V input and drive capability (112-pin package)
  - Up to two dedicated 3.3 V input only lines (IRQ, XIRQ)
• Development support
  - Single-wire background debug™ mode (BDM)
  - On-chip hardware breakpoints
  - Enhanced DBG debug features


Pinout

Connection Diagram


Specifications

Num Rating Symbol Min Max Unit
1 I/O, Regulator and Analog Supply Voltage VDD5 0.3 4.5 V
2 Digital Logic Supply Voltage(1) VDD 0.3 3.0 V
3 PLL Supply Voltage 1 VDDPLL 0.3 3.0 V
4 Voltage difference VDDX to VDDR and VDDA VDDX 0.3 0.3 V
5 Voltage difference VSSX to VSSR and VSSA VSSX 0.3 0.3 V
6 Digital I/O Input Voltage VIN 0.3 6.5 V
7 Analog Reference VRH, VRL 0.3 6.5 V
8 XFC, EXTAL, XTAL inputs VILV 0.3 3.0 V
9 TEST input VTEST 0.3 10.0 V
10 Instantaneous Maximum Current
Single pin limit for all digital I/O pins (2)		 ID 25 +25 mA
11 Instantaneous Maximum Current
Single pin limit for XFC, EXTAL, XTAL(3)		 IDL 25 +25 mA
12 Instantaneous Maximum Current
Single pin limit for TEST(4)		 IDT 0.25 0 mA
13 Operating Temperature Range (packaged) TA 40 105 °C
14 Operating Temperature Range (junction) TJ 40 125 °C
15 Storage Temperature Range Tstg 65 155 °C



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