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MC9S12KC128

Features: •HCS12 Core16-bit HCS12 CPUi. Upward compatible with M68HC11 instruction setii. Interrupt stacking and programmer's model identical to M68HC11iii. Instruction queueiv. Enhanced indexed addressingMEBI (Multiplexed External Bus Interface)MMC (Memory Map and Interface)INT (Interrupt C...

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MC9S12KC128: Features: •HCS12 Core16-bit HCS12 CPUi. Upward compatible with M68HC11 instruction setii. Interrupt stacking and programmer's model identical to M68HC11iii. Instruction queueiv. Enhanced index...

MC9S12KC128 Data Sheet

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Part Number:
MC9S12KC128
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/27

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Product Details

Description



Features:

•HCS12 Core
16-bit HCS12 CPU
i. Upward compatible with M68HC11 instruction set
ii. Interrupt stacking and programmer's model identical to M68HC11
iii. Instruction queue
iv. Enhanced indexed addressing
MEBI (Multiplexed External Bus Interface)
MMC (Memory Map and Interface)
INT (Interrupt Controller)
DBG (Debugger)
BDM (Background Debug Mode)
•Oscillator
4Mhz to 16Mhz frequency range
Pierce with amplitude loop control
Clock monitor
•Clock and Reset Generator (CRG)
Phase-locked loop clock frequency multiplier
Self Clock mode in absence of external clock
COP watchdog
Real Time interrupt (RTI)
•Memory
32K, 64K, 128K or 256K Byte Flash EEPROM
i. Internal program/erase voltage generation
ii. Security and Block Protect bits
iii. Hamming Error Correction Coding (ECC)
1K, 2K or 4K Byte EEPROM
2K, 4K, 6K, 8K or 12K Byte static RAM
Single-cycle misaligned word accesses without wait states
•Analog-to-Digital Converter(s) (ADC)
One 16-channel module with 10-bit resolution except for MC9S12KT256 and MC9S12KG256
Two 8-channel module with 10-bit resolution for MC9S12KT256 and MC9S12KG256
External conversion trigger capability
•8-channel Timer (TIM)
Programmable input capture or output compare channels
Simple PWM mode
Counter Modulo Reset
External Event Counting
Gated Time Accumulation
•8-channel Pulse Width Modulator (PWM)
Programmable period and duty cycle per channel
8-bit 8-channel or 16-bit 4-channel
Edge and center aligned PWM signals
Emergency shutdown input
•Two or Three 1M bit per second, CAN 2.0 A, B software compatible modules
Five receive and three transmit buffers
Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit
Four separate interrupt channels for Rx, Tx, error and wake-up
Low-pass filter wake-up function
Loop-back for self test operation
•Serial interfaces
Two asynchronous serial communication interface (SCI)
Three synchronous serial peripheral interface (SPI)
Inter-IC Bus (IIC)
•Internal 2.5V Regulator
Input voltage range from 3.15V to 5.5V
Low power mode capability
Low Voltage Reset (LVR) and Low Voltage Interrupt (LVI)
•20 key wake up inputs
Rising or falling edge triggered interrupt capability
Digital filter to prevent short pulses from triggering interrupts
Programmable pull ups and pull downs
•Operating frequency for ambient temperatures (TA -40 to 125)
50MHz equivalent to 25MHz Bus Speed
•112-Pin LQFP, 100-Pin LQFP, or 80-Pin QFP package
I/O lines with 3.3V/5V input and drive capability
3.3V/5V A/D converter inputs


Specifications

Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device.

This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS5 or VDD5).
Num Rating Symbol Min Max Unit
1 I/O, Regulator and Analog Supply Voltage VDD5 -0.3 6.5 V
2 Internal Logic Supply Voltage1 VDD -0.3 3.0 V
3 PLL Supply Voltage (1) VDDPLL -0.3 3.0 V
4 Voltage difference VDDX to VDDR and VDDA VDDX -0.3 0.3 V
5 Voltage difference VSSX to VSSR and VSSA VSSX -0.3 0.3 V
6 Digital I/O Input Voltage VIN -0.3 6.5 V
7 Analog Reference VRH, VRL -0.3 6.5 V
8 XFC, EXTAL, XTAL inputs VILV -0.3 3.0 V
9 TEST input VTEST -0.3 10.0 V
10 Instantaneous Maximum Current
Single pin limit for all digital I/O pins 2		 ID -25 +25 mA
11 Instantaneous Maximum Current
Single pin limit for XFC, EXTAL, XTAL3		 IDL -25 +25 mA
12 Instantaneous Maximum Current
Single pin limit for TEST4		 IDT -0.25 0 mA
13 Operating Temperature Range (packaged) TA 40 125
14 Operating Temperature Range (junction) TJ 40 140
15 Storage Temperature Range Tstg 65 155



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