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MC9S12DJ128

Features: • HCS12 Core 16-bit HCS12 CPUi. Upward compatible with M68HC11 instruction setii. Interrupt stacking and programmer's model identical to M68HC11iii.20-bit ALUiv. Instruction queuev. Enhanced indexed addressing MEBI (Multiplexed External Bus Interface) MMC (Module Mapping Control) I...

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SeekIC No. : 004417417 Detail

MC9S12DJ128: Features: • HCS12 Core 16-bit HCS12 CPUi. Upward compatible with M68HC11 instruction setii. Interrupt stacking and programmer's model identical to M68HC11iii.20-bit ALUiv. Instruction queuev. ...

MC9S12DJ128 Data Sheet

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Part Number:
MC9S12DJ128
Supply Ability:
5000

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Product Details

Description



Features:

• HCS12 Core
16-bit HCS12 CPU
i. Upward compatible with M68HC11 instruction set
ii. Interrupt stacking and programmer's model identical to M68HC11
iii.20-bit ALU
iv. Instruction queue
v. Enhanced indexed addressing
MEBI (Multiplexed External Bus Interface)
MMC (Module Mapping Control)
INT (Interrupt control)
BKP (Breakpoints)
BDM (Background Debug Module)
• CRG (Clock and Reset Generator)
Choice of low current Colpitts oscillator or standard Pierce Oscillator
PLL
COP watchdog
real time interrupt
clock monitor
• 8-bit and 4-bit ports with interrupt functionality
Digital filtering
Programmable rising or falling edge trigger
 Memory
128K Flash EEPROM
2K byte EEPROM
8K byte RAM
  Two 8-channel Analog-to-Digital Converters
10-bit resolution
External conversion trigger capability
 Three 1M bit per second, CAN 2.0 A, B software compatible modules
Five receive and three transmit buffers
Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8x8bit
Four separate interrupt channels for Rx, Tx, error and wake-up
Low-pass filter wake-up function
Loop-back for self test operation
 Enhanced Capture Timer
16-bit main counter with 7-bit prescaler
8 programmable input capture or output compare channels
Four 8-bit or two 16-bit pulse accumulators
• 8 PWM channels
Programmable period and duty cycle
8-bit 8-channel or 16-bit 4-channel
Separate control for each pulse width and duty cycle
Center-aligned or left-aligned outputs
Programmable clock select logic with a wide range of frequencies
Fast emergency shutdown input
Usable as interrupt inputs
• Serial interfaces
Two asynchronous Serial Communications Interfaces (SCI)
Two Synchronous Serial Peripheral Interface (SPI)
Byteflight
• Byte Data Link Controller (BDLC)


Pinout

Connection Diagram


Description

This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. MC9S12DG256 is built from the signal description sections of the Block User Guides of the individual IP blocks on the device.


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