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MC9S12D

Features: Not all features listed here are available in all configurations.Additional information about D and B family inter-operability is given in:EB386 HCS12 D-Family Compatibility Considerations andEB388 Using the HCS12 D-Family as a development platform for the HCS12 B family • 16-bi...

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SeekIC No. : 004417406 Detail

MC9S12D: Features: Not all features listed here are available in all configurations.Additional information about D and B family inter-operability is given in:EB386 HCS12 D-Family Compatibility Consideration...

MC9S12D Data Sheet

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Part Number:
MC9S12D
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Description



Features:

Not all features listed here are available in all configurations.
Additional information about D and B family inter-operability is given in:
EB386 "HCS12 D-Family Compatibility Considerations" and
EB388 "Using the HCS12 D-Family as a development platform for the HCS12 B family"
• 16-bit CPU12
- Upward compatible with M68HC11 instruction set
- Interrupt stacking and programmer's model identical to M68HC11
- HCS12 Instruction queue
- Enhanced indexed addressing
• Multiplexed bus
- Single chip or expanded
- 16 address/16 data wide or 16 address/8 data narrow modes
- External address space 1MByte for Data and Program space (112 pin package only)
• Wake-up interrupt inputs depending on the package option
- 8-bit port H
- 2-bit port J1:0
- 2-bit port J7:6 shared with IIC, CAN4 and CAN0 module
- 8-bit port P shared with PWM or SPI1,2
• Memory options
- 32K, 64K, 128K, 256K, 512K Byte Flash EEPROM
- 1K, 2K, 4K Byte EEPROM
- 2K, 4K, 8K, 12K, 14K Byte RAM
• Analog-to-Digital Converters
- One or two 8-channel modules with 10-bit resolution depending on the package option
- External conversion trigger capability
• Up to five 1M bit per second, CAN 2.0 A, B software compatible modules
- Five receive and three transmit buffers
- Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit
- Four separate interrupt channels for Receive, Transmit, Error and Wake-up
- Low-pass filter wake-up function in STOP mode
- Loop-back for self test operation
• Enhanced Capture Timer (ECT)
- 16-bit main counter with 7-bit prescaler
- 8 programmable input capture or output compare channels; 4 of the 8 input captures with buffer
- Input capture filters and buffers, three successive captures on four channels, or two captures on four channels with a capture/compare selectable on the remaining four
- Four 8-bit or two 16-bit pulse accumulators
- 16-bit modulus down-counter with 4-bit prescaler
- Four user-selectable delay counters for signal filtering
• 8 PWM channels with programmable period and duty cycle (7 channels on 80 Pin Packages)
- 8-bit, 8-channel or 16-bit, 4-channel
- Separate control for each pulse width and duty cycle
- Center- or left-aligned outputs
- Programmable clock select logic with a wide range of frequencies
• Serial interfaces
- Two asynchronous serial communications interfaces (SCI)
- Up to three synchronous serial peripheral interfaces (SPI)
- IIC
• SAE J1850 Compatible Module (BDLC)
- 10.4 kbps Variable Pulse Width format
- Byte level receive and transmit
- 4x receive mode supported
• SIM (System Integration Module)
- CRG (windowed COP watchdog, real time interrupt, clock monitor, clock generation and reset)
- MEBI (multiplexed external bus interface)
- INT (interrupt control)
• Clock generation
- Phase-locked loop clock frequency multiplier
- Limp home mode in absence of external clock
- Clock Monitor
- Low power 0.5 to 16 MHz crystal oscillator reference clock
• Operating frequency for ambient temperatures TA -40  <= TA <= 125
- 50MHz equivalent to 25MHz Bus Speed for single chip
40MHz equivalent to 20MHz Bus Speed in expanded bus modes.
• Internal 5V to 2.5V Regulator
• 112-Pin LQFP or 80-Pin QFP package
- I/O lines with 5V input and drive capability
- 5V A/D converter inputs and 5V I/O
- 2.5V logic supply
• Development support
- Single-wire background debug™ mode (BDM)
- On-chip hardware breakpoints


Pinout

Connection Diagram


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