MC9S08QE128

• 8-Bit HCS08 Central Processor Unit (CPU)
Up to 50.33-MHz HCS08 CPU from 3.6V to 2.1V, and 20-MHz CPU at 2.1V to 1.8V across temperature range
HC08 instruction set with added BGND instruction
Support for up to 32 interrupt/reset sources
• On-Chip Memory
Flash read/program/erase over full operating voltage and temperature
Random-access memory (RAM)
Security circuitry to prevent unauthorized access to RAM and flash contents
• Power-Saving Modes
Two low power stop modes; reduced power wait mode
Peripheral clock enable register can disable clocks to unused modules, reducing currents; allows clocks to remain enabled to specific peripherals in stop3 mode
Very low power external oscillator can be used in stop3 mode to provide accurate clock to active peripherals
Very low power real time counter for use in run, wait,and stop modes with internal and external clock sources
6s typical wake up time from stop modes
• Clock Source Options
Oscillator (XOSC) - Loop-control Pierce oscillator;Crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz
Internal Clock Source (ICS) - FLL controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation; supports CPU freq. from 2 to 50.33 MHz
• System Protection
Watchdog computer operating properly (COP) reset with option to run from dedicated 1-kHz internal clock source or bus clock
Low-voltage detection with reset or interrupt; selectable trip points
Illegal opcode detection with reset
Flash block protection
• Development Support
Single-wire background debug interface
Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints)
On-chip in-circuit emulator (ICE) debug module containing two comparators and nine trigger modes.Eight deep FIFO for storing change-of-flow addressesand event-only data. Debug module supports both tag and force breakpoints.
• ADC - 24-channel, 12-bit resolution; 2.5 s conversion time; automatic compare function; 1.7 mV/°C temperature sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6V to 1.8V
• ACMPx - Two analog comparators with selectable interrupt on rising, falling, or either edge of comparator output; compare option to fixed internal bandgap reference voltage; outputs can be optionally routed to TPM module;operation in stop3
• SCIx - Two SCIs with full duplex non-return to zero (NRZ); LIN master extended break generation; LIN slave extended break detection; wake up on active edge
• SPIx- Two serial peripheral interfaces with Full-duplex or single-wire bidirectional; Double-buffered transmit and receive; MSB-first or LSB-first shifting
• IICx-Two IICs with; Up to 100 kbps with maximum bus loading; Multi-master operation; Programmable slave address; Interrupt driven byte-by-byte data transfer;supports broadcast mode and 10 bit addressing
• TPMx - One 6-channel and two 3-channel; Selectable input capture, output compare, or buffered edge- or center-aligned PWMs on each channel
• RTC - 8-bit modulus counter with binary or decimal based prescaler; External clock source for precise time base, time-of-day, calendar or task scheduling functions;Free running on-chip low power oscillator (1 kHz) for cyclic wake-up without external components
• Input/Output
70 GPIOs and 1 input-only and 1 output-only pin
16 KBI interrupts with selectable polarity
Hysteresis and configurable pull-up device on all input pins; Configurable slew rate and drive strength on all output pins.
SET/CLR registers on 16 pins (PTC and PTE)

1 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (V_DD) and negative (V_SS) clamp voltages, then use the larger of the two resistance values.
2 All functional non-supply pins are internally clamped to V_SS and V_DD.