Features: ·Implements ATM Layer Functions for Broadband ISDN According to ATM Forum UNI 4.0 and TM 4.0 SpeciÞcations, ITU Recommendations, and Bellcore Recommendations·Provides ABR Relative Rate Marking and EFCI Marking According to TM 4.0·Selective Discard CLP = 1 (or CLP = 0+1) Flow on Sel...
MC92501: Features: ·Implements ATM Layer Functions for Broadband ISDN According to ATM Forum UNI 4.0 and TM 4.0 SpeciÞcations, ITU Recommendations, and Bellcore Recommendations·Provides ABR Relative Ra...
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·Implements ATM Layer Functions for Broadband ISDN According to ATM Forum UNI 4.0 and TM 4.0 SpeciÞcations, ITU Recommendations, and Bellcore Recommendations
·Provides ABR Relative Rate Marking and EFCI Marking According to TM 4.0
·Selective Discard CLP = 1 (or CLP = 0+1) Flow on Selected Connections
·UTOPIA Level 2 PHY Interface and UTOPIA ATM Layer Interface
·Supports Both Partial Packet Discard (PPD) and Early Packet Discard (EPD)
·Change ABR RM Cell Priority
·Support for CLP Transparency
Symbol |
Parameter |
Value/Value Range |
Unit |
VDD |
DC Supply Voltage |
- 0.5 to 3.8 |
V |
Vin 3 |
DC Input Voltage (5 V Tolerant) |
- 0.5 to 5.8 |
V |
Vout 3,4 |
DC Output Voltage |
- 0.5 to VDD +0.5 |
V |
I |
DC Current Drain per Pin, Any Single Input or Output |
± 50 |
mA |
I |
DC Current Drain VDD and VSS Pins |
± 100 |
mA |
Tstg |
Storage Temperature |
- 65 to 150 |
°C |
TL |
Lead Temperature (10-Second Soldering) |
300 |
°C |
The ATM Cell Processor (MC92501) is an Asynchronous Transfer Mode (ATM) layer device composed of dedicated high-performance ingress and egress cell processors combined with UTOPIA Level 2-compliant physical (PHY) and switch interface ports (see Block Diagram). The MC92501 is a second generation ATM cell processor in MotorolaÕs 92500 series. This document provides information on the new features offered by the second generation ATM cell processor. This document, combined with MC92500/D, provides the complete speciÞcation for the ATM cell processor.