PinoutSpecifications Symbol Parameter Value Condition Unit VCC DC Supply Voltage 0.5 to +7.0 V VI DC Input Voltage 0.5 VI VCC + 0.5V V VO DC Output Voltage 0.5 VO VCC + 0.5 Output in HIGH or LOW State V IIK DC Input Diode Current 20 VI = 0.5V mA +20 VI =...
MC74LVQ646: PinoutSpecifications Symbol Parameter Value Condition Unit VCC DC Supply Voltage 0.5 to +7.0 V VI DC Input Voltage 0.5 VI VCC + 0.5V V VO DC Output Voltage 0.5 VO VCC ...
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Features: Operating range: 38 to 47 Gb/s (min.) (note)Signal regeneration with full-rate clock sig...
Symbol | Parameter | Value | Condition | Unit |
VCC | DC Supply Voltage | 0.5 to +7.0 | V | |
VI | DC Input Voltage | 0.5 VI VCC + 0.5V | V | |
VO | DC Output Voltage | 0.5 VO VCC + 0.5 | Output in HIGH or LOW State | V |
IIK | DC Input Diode Current | 20 | VI = 0.5V | mA |
+20 | VI = VCC + 0.5V | mA | ||
IOK | DC Output Diode Current | 20 | VO = 0.5V | mA |
+20 | VI = VCC + 0.5V | mA | ||
IO | DC Output Source/Sink Current | +50 | mA | |
ICC | DC Supply Current Per Supply Pin | ±400 | mA | |
IGND | DC Ground Current Per Ground Pin | ±400 | mA | |
TSTG | Storage Temperature Range | 65 to +150 | °C |
The MC74LVQ646 is a high performance, noninverting octal transceiver/registered transceiver operating from a 2.7 to 3.6V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. The MC74LVQ646 is suitable for memory address driving and all TTL level bus oriented transceiver applications.
Data of MC74LVQ646 on the A or B bus will be clocked into the registers as the appropriate clock pin goes from a LOWtoHIGH logic level. Output Enable (OE) and DIR pins of MC74LVQ646 are provided to control the transceiver outputs. In the transceiver mode, data present at the high impedance port may be stored in either the A or the B register or in both. The select controls of MC74LVQ646 (SBA, SAB) can multiplex stored and realtime (transparent mode) data. The direction control (DIR) determines which bus will receive data when the enable OE is active LOW. In the isolation mode (OE HIGH), A data may be stored in the B register or B data may be stored in the A register. Only one of the two buses, A or B, may be driven at one time.