Features: • Designed for 2.7 to 3.6V VCC Operation• 5V Tolerant - Interface Capability With 5V TTL Logic• Supports Live Insertion and Withdrawal• IOFF Specification Guarantees High Impedance When VCC = 0V• LVTTL Compatible• LVCMOS Compatible• 24mA Balanced...
MC74LCX373: Features: • Designed for 2.7 to 3.6V VCC Operation• 5V Tolerant - Interface Capability With 5V TTL Logic• Supports Live Insertion and Withdrawal• IOFF Specification Guarantee...
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Features: Operating range: 38 to 47 Gb/s (min.) (note)Signal regeneration with full-rate clock sig...
Symbol | Parameter | Value | Condition | Unit |
VCC | DC Supply Voltage | 0.5 to +7.0 | V | |
VI | DC Input Voltage | 0.5 VI +7.0 | V | |
VO | DC Output Voltage | 0.5 VO +7.0 | Output in 3State | V |
0.5 VO VCC + 0.5 | Note 1. | V | ||
IIK | DC Input Diode Current | 50 | VI < GND | mA |
IOK | DC Output Diode Current | 50 | VO < GND | mA |
+50 | VO > VCC | mA | ||
IO | DC Output Source/Sink Current | +50 | mA | |
ICC | DC Supply Current Per Supply Pin | ±100 | mA | |
IGND | DC Ground Current Per Ground Pin | ±100 | mA | |
TSTG | Storage Temperature Range | 65 to +150 | °C |
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolutemaximumrated conditions is not implied.
1. Output in HIGH or LOW State. IO absolute maximum rating must be observed.
The MC74LCX373 is a high performance, noninverting octal transparent latch operating from a 2.7 to 3.6V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A VI specification of 5.5V allows MC74LCX373 inputs to be safely driven from 5V devices.
The MC74LCX373 contains 8 Dtype latches with 3state outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition, the latches of MC74LCX373 are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGHtoLOW transition of LE. The 3state standard outputs are controlled by the Output Enable (OE) input. When OE is LOW, the standard outputs are enabled. When OE is HIGH, the standard outputs are in the high impedance state, but this does not interfere with new data entering into the latches.