PinoutSpecifications Symbol Symbol Value Condition Unit VCC DC Supply Voltage 0.5 to +7.0 V VI DC Input Voltage 0.5VI+7.0 V VO DC Output Voltage 0.5VO+7.0 Output in 3State V 0.5VOVCC + 0.5 Note 1. V IIK DC Input D...
MC74LCX16373: PinoutSpecifications Symbol Symbol Value Condition Unit VCC DC Supply Voltage 0.5 to +7.0 V VI DC Input Voltage 0.5VI+7.0 V VO DC Output Vo...
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Features: Operating range: 38 to 47 Gb/s (min.) (note)Signal regeneration with full-rate clock sig...
Symbol |
Symbol |
Value |
Condition |
Unit |
VCC |
DC Supply Voltage |
0.5 to +7.0 |
V | |
VI |
DC Input Voltage |
0.5VI+7.0 |
V | |
VO
|
DC Output Voltage |
0.5VO+7.0 |
Output in 3State |
V |
0.5VOVCC + 0.5 |
Note 1. |
V | ||
IIK |
DC Input Diode Current |
-50 |
VI < GND |
mA |
IOK
|
DC Output Diode Current |
-50 |
VO < GND |
mA |
+50 |
VO > VCC |
mA | ||
IO |
DC Output Source/Sink Current |
±50 |
mA | |
ICC |
DC Supply Current Per Supply Pin |
±100 |
mA | |
IGND |
DC Ground Current Per Ground Pin |
±100 |
mA | |
TSTG |
Storage Temperature Range |
65 to +150 |
°C |
The MC74LCX16373 is a high performance, noninverting 16bit transparent latch operating from a 2.7 to 3.6V supply. The device is byte controlled. Each byte has separate Output Enable and Latch Enable inputs. These control pins can be tied together for full 16bit operation. High impedance TTL compatible inputs significantly reduce current
loading to input drivers while TTL compatible outputs offer improved switching noise performance. A VI specification of 5.5V allows MC74LCX16373 inputs to be safely driven from 5V devices.
The MC74LCX16373 contains 16 Dtype latches with 3state 5Vtolerant outputs. When the Latch Enable (LEn) inputs are HIGH, data on the Dn inputs enters the latches. In this condition, the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGHtoLOW transition of LE. The 3state outputs are controlled by the Output Enable (OEn) inputs. When OE is LOW, the outputs are enabled. When OE is HIGH, the standard outputs are in the high impedance state, but this does not interfere with new data entering into the latches.
• Designed for 2.7 to 3.6V VCC Operation
• 5.4ns Maximum tpd
• 5V Tolerant - Interface Capability With 5V TTL Logic
• Supports Live Insertion and Withdrawal
• IOFF Specification Guarantees High Impedance When VCC = 0V
• LVTTL Compatible
• LVCMOS Compatible
• 24mA Balanced Output Sink and Source Capability
• Near Zero Static Supply Current in All Three Logic States (20A) Substantially Reduces System Power Requirements
• Latchup Performance Exceeds 500mA
• ESD Performance: Human Body Model >2000V; Machine Model >200V