MC74HC533A

• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 A
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard No. 7A
• Chip Complexity: 256 FETs or 64 Equivalent Gates

The MC54/74HC533A is identical in pinout to the LS533. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
 
These latches of MC74HC533A appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. The Data appears at the outputs in inverted form. When Latch Enable goes low, data meeting the setup and hold time becomes latched.

The Output Enable input does not affect the state of the latches, but when Output Enable is high, all device outputs are forced to the high-impedance state. Thus, data of MC74HC533A may be latched even when the outputs are not enabled.

The HC533A is identical in function to the HC563 but has the data inputs on the opposite side of the package from the outputs to facilitate PC board layout.

MC74HC533A is similar in function to the HC373A, which has noninvertingoutputs.